Datasheet > CY62167E_13

CY62167E_13

更新时间： 2024-11-20 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	515K
描述
16-Mbit (1 M x 16 / 2 M x 8) Static RAM

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CY62167E_13 数据手册

CY62167E MoBL^®

16-Mbit (1 M × 16 / 2 M × 8) Static RAM

16-Mbit (1

M × 16 / 2 M × 8) Static RAM

and BLE are HIGH). The input and output pins (I/O₀through

I/O₁₅) are placed in a high impedance state when:

Features

■ Configurable as 1 M × 16 or as 2 M × 8 SRAM

■ Very high speed: 45 ns

■ The device is deselected (CE₁HIGH or CE₂LOW)

■ Outputs are disabled (OE HIGH)

■ Wide voltage range: 4.5 V to 5.5 V

■ Both byte high enable and byte low enable are disabled (BHE,

BLE HIGH) or

■ Ultra low standby power

❐ Typical standby current: 1.5 µA

❐ Maximum standby current: 12 µA

■ A write operation is in progress (CE₁LOW, CE₂HIGH, and WE

LOW)

■ Ultra low active power

❐ Typical active current: 2.2 mA at f = 1 MHz

To write to the device, take chip enables (CE₁LOW and CE₂

HIGH) and write enable (WE) input LOW. If byte low enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

■ Easy memory expansion with CE₁, CE₂, and OE features

■ Automatic power-down when deselected

■ CMOS for optimum speed and power

written into the location specified on the address pins (A₀through

₁₉). If byte high enable (BHE) is LOW, then data from the I/O

pins (I/O₈through I/O₁₅) is written into the location specified on

the address pins (A₀through A₁₉).

■ Offered in 48-pin TSOP I package

To read from the device, take chip enables (CE₁LOW and CE₂

HIGH) and output enable (OE) LOW while forcing the write

enable (WE) HIGH. If byte low enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O₀to I/O₇. If byte high enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See Truth Table on page 12

for a complete description of read and write modes.

Functional Description

The CY62167E is a high performance CMOS static RAM

organized as 1 M words by 16-bits/2 M words by 8-bits. This

device features advanced circuit design to provide an ultra low

active current. This is ideal for providing More Battery Life

(MoBL^®) in portable applications. The device also has an

automatic power down feature that reduces power consumption

when addresses are not toggling. Place the device into standby

mode when deselected (CE₁HIGH, or CE₂LOW, or both BHE

The CY62167E device is suitable for interfacing with processors

that have TTL I/P levels. It is not suitable for processors that

require CMOS I/P levels. Please see Electrical Characteristics

on page 4 for more details and suggested alternatives.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

1 M × 16 / 2 M × 8

I/O₀–I/O₇

RAM ARRAY

A ₃

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BYTE

BHE

CE₂

POWER DOWN

CIRCUIT

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-15607 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 10, 2013

12 3 4 5 6 7...17

中文翻译

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与CY62167E_13相关器件

型号	品牌	获取价格	描述	数据表
CY62167ELL	CYPRESS	获取价格	16-Mbit (1 M × 16 / 2 M × 8) Static RAM
CY62167ELL-45ZXI	CYPRESS	获取价格	16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167ELL-45ZXI	INFINEON	获取价格	Asynchronous SRAM
CY62167ELL-45ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167ESL-55FNXI	CYPRESS	获取价格	Standard SRAM, 1MX16, 55ns, CMOS, PBGA60, WLCSP-60
CY62167EV18	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167EV18_11	CYPRESS	获取价格	16 Mbit (1M x 16) Static RAM Automatic power down when deselected
CY62167EV18LL-45BVXI	CYPRESS	获取价格	Standard SRAM, 1MX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV18LL-55BAXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVI	CYPRESS	获取价格	16 Mbit (1M x 16) Static RAM

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