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CY62167EV18LL-45BVXI

更新时间： 2024-11-24 15:43:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
11页 489K
描述
Standard SRAM, 1MX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

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CY62167EV18LL-45BVXI 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA,
针数：48Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.71Is Samacsys：N
最长访问时间：45 nsJESD-30 代码：R-PBGA-B48
长度：8 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：2.25 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmBase Number Matches：1

CY62167EV18LL-45BVXI 数据手册

 浏览型号CY62167EV18LL-45BVXI的Datasheet PDF文件第2页浏览型号CY62167EV18LL-45BVXI的Datasheet PDF文件第3页浏览型号CY62167EV18LL-45BVXI的Datasheet PDF文件第4页浏览型号CY62167EV18LL-45BVXI的Datasheet PDF文件第5页浏览型号CY62167EV18LL-45BVXI的Datasheet PDF文件第6页浏览型号CY62167EV18LL-45BVXI的Datasheet PDF文件第7页 
CY62167EV18  
MoBL®  
PRELIMINARY  
16-Mb (1M x 16) Static RAM  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE1HIGH or CE2  
LOW), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a write operation (CE1 LOW, CE2 HIGH and WE  
LOW).  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 1.65V–2.25V  
• Ultra low standby power  
— Typical standby current: 1.5 µA  
— Maximum standby current: 8.5 µA  
• Ultra-low active power  
— Typical active current: 2.2 mA @ f = 1 MHz  
To writ to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A19). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A19).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Offered in Pb-free 48-ball BGA package  
To read from the device, take Chip Enables (CE1 LOW and  
CE2 HIGH) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description[1]  
The CY62167EV18 is a high-performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
1M × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-Down  
Circuit  
CE2  
BHE  
BLE  
CE  
1
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05447 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 14, 2006  
1234567...11

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