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CY62167EV18LL-55BVIT

更新时间： 2024-11-21 14:56:19
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
17页 295K
描述
Asynchronous SRAM

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CY62167EV18LL-55BVIT 数据手册

 浏览型号CY62167EV18LL-55BVIT的Datasheet PDF文件第2页浏览型号CY62167EV18LL-55BVIT的Datasheet PDF文件第3页浏览型号CY62167EV18LL-55BVIT的Datasheet PDF文件第4页浏览型号CY62167EV18LL-55BVIT的Datasheet PDF文件第5页浏览型号CY62167EV18LL-55BVIT的Datasheet PDF文件第6页浏览型号CY62167EV18LL-55BVIT的Datasheet PDF文件第7页 
CY62167EV18 MoBL®  
16-Mbit (1 M × 16) Static RAM  
16-Mbit (1  
M × 16) Static RAM  
automatic power down feature that reduces power consumption  
by 99 percent when addresses are not toggling. Place the device  
into standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input and output pins (I/O0  
through I/O15) are placed in a high impedance state when: the  
device is deselected (CE1HIGH or CE2 LOW); outputs are  
disabled (OE HIGH); both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH); and a write operation is  
in progress (CE1 LOW, CE2 HIGH and WE LOW).  
Features  
■ Very high speed: 55 ns  
■ Wide voltage range: 1.65 V to 2.25 V  
■ Ultra low standby power  
❐ Typical standby current: 1.5 A  
❐ Maximum standby current: 12 A  
■ Ultra low active power  
❐ Typical active current: 2.2 mA at f = 1 MHz  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is  
written into the location specified on the address pins (A0 through  
A19). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(I/O8 through I/O15) is written into the location specified on the  
address pins (A0 through A19).  
■ Easy memory expansion with CE1, CE2, and OE features  
■ Automatic power down when deselected  
■ CMOS for optimum speed and power  
■ Offered in Pb-free 48-ball very fine ball grid array (VFBGA)  
packages  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See the Truth Table on page  
11 for a complete description of read and write modes.  
Functional Description  
The CY62167EV18 is a high performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has an  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
1M × 16  
RAM ARRAY  
I/O0–I/O7  
A 4  
I/O8–I/O15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
CE2  
CE  
1
PowerDown  
Circuit  
1
OE  
BHE  
BLE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05447 Rev. *O  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 16, 2015  
1234567...17

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与CY62167EV18LL-55BVIT相关器件

型号 品牌 获取价格 描述 数据表
CY62167EV18LL-55BVXI CYPRESS

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 		16-Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVXI INFINEON

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 		Asynchronous SRAM
CY62167EV18LL-55BVXIT CYPRESS

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 		Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV18LL-55BVXIT INFINEON

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CY62167EV30 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30_09 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30_10 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30_11 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM Automatic power-down when deselected
CY62167EV30_12 CYPRESS

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 		16-Mbit (1 M × 16 / 2 M × 8) Static RAM
CY62167EV30LL CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM

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