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CY62167EV30LL-45BVXA PDF预览

CY62167EV30LL-45BVXA

更新时间： 2024-11-05 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
14页 492K
描述
16-Mbit (1M x 16 / 2M x 8) Static RAM

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CY62167EV30LL-45BVXA 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA48,6X8,30针数：48
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.3
Is Samacsys：N最长访问时间：45 ns
备用内存宽度：8I/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1 mm
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.03 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：6 mmBase Number Matches：1

CY62167EV30LL-45BVXA 数据手册

 浏览型号CY62167EV30LL-45BVXA的Datasheet PDF文件第2页浏览型号CY62167EV30LL-45BVXA的Datasheet PDF文件第3页浏览型号CY62167EV30LL-45BVXA的Datasheet PDF文件第4页浏览型号CY62167EV30LL-45BVXA的Datasheet PDF文件第5页浏览型号CY62167EV30LL-45BVXA的Datasheet PDF文件第6页浏览型号CY62167EV30LL-45BVXA的Datasheet PDF文件第7页 
CY62167EV30 MoBL®  
16-Mbit (1M x 16 / 2M x 8) Static RAM  
low active current. Ultra low active current is ideal for providing  
More Battery Life™ (MoBL®) in portable applications such as  
cellular telephones. The device also has an automatic power  
down feature that reduces power consumption by 99 percent  
when addresses are not toggling. Place the device into standby  
mode when deselected (CE1 HIGH or CE2 LOW or both BHE and  
Features  
■ TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM  
■ Very High Speed: 45 ns  
■ Temperature Ranges  
BLE are HIGH). The input and output pins (I/O0 through I/O15  
)
❐ Industrial: –40°C to +85°C  
❐ Automotive-A: –40°C to +85°C  
are placed in a high impedance state when: the device is  
deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH), or a write operation is in progress (CE1 LOW,  
CE2 HIGH and WE LOW).  
■ Wide Voltage Range: 2.20V to 3.60V  
■ Ultra Low Standby Power  
❐ Typical standby current: 1.5 μA  
❐ Maximum standby current: 12 μA  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is  
written into the location specified on the address pins (A0 through  
A19). If Byte High Enable (BHE) is LOW, then data from the I/O  
pins (I/O8 through I/O15) is written into the location specified on  
the address pins (A0 through A19).  
■ Ultra Low Active Power  
❐ Typical active current: 2.2 mA at f = 1 MHz  
■ Easy Memory Expansion with CE1, CE2, and OE Features  
■ Automatic Power Down when Deselected  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See the “Truth Table” on  
page 9 for a complete description of read and write modes.  
■ CMOS for Optimum Speed and Power  
■ Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I  
Packages  
Functional Description  
The CY62167EV30 is a high performance CMOS static RAM  
organized as 1M words by 16 bits or 2M words by 8 bits. This  
device features an advanced circuit design that provides an ultra  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
1M × 16 / 2M x 8  
RAM Array  
IO0–IO7  
A 4  
IO8–IO15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE  
CE2  
1
PowerDown  
Circuit  
CE  
1
OE  
BHE  
BLE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05446 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 17, 2009  
[+] Feedback  
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CY62167EV30LL-45BVXA 替代型号

型号 品牌 替代类型 描述 数据表
CY62167EV30LL-45BVXIT CYPRESS

完全替代

 Standard SRAM, 1MX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-48
CY62167EV30LL-45BVI CYPRESS

完全替代

 16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30LL-45BVXI CYPRESS

完全替代

 16-Mbit (1M x 16 / 2M x 8) Static RAM

与CY62167EV30LL-45BVXA相关器件

型号 品牌 获取价格 描述 数据表
CY62167EV30LL-45BVXAT CYPRESS

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 		Standard SRAM, 1MX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV30LL-45BVXAT INFINEON

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 		Asynchronous SRAM
CY62167EV30LL-45BVXI CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30LL-45BVXI INFINEON

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 		Asynchronous SRAM
CY62167EV30LL-45BVXIT CYPRESS

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 		Standard SRAM, 1MX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-48
CY62167EV30LL-45BVXIT INFINEON

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 		Asynchronous SRAM
CY62167EV30LL-45ZXA CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30LL-45ZXA INFINEON

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 		Asynchronous SRAM
CY62167EV30LL-45ZXAT CYPRESS

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 		Standard SRAM, 1MX16, 45ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, T
CY62167EV30LL-45ZXAT INFINEON

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 		Asynchronous SRAM

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