Datasheet > CY62167G30-55BVXET

CY62167G30-55BVXET

更新时间： 2023-09-03 20:30:57

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
19页	519K
描述
Asynchronous SRAM

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数据手册

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CY62167G Automotive

16-Mbit (1M Words × 16-Bit) Static RAM

with Error-Correcting Code (ECC)

16-Mbit (1M Words

× 16-Bit) Static RAM with Error-Correcting Code (ECC)

Data writes are performed by asserting the Write Enable input

(WE) LOW, and providing the data and address on device data

(I/O₀through I/O₁₅) and address (A₀through A₁₉) pins

respectively. The Byte High/Low Enable (BHE, BLE) inputs

control byte writes, and write data on the corresponding I/O lines

Features

■ AEC-Q100 qualified

■ Ultra-low standby power

❐ Typical standby current: 5.5 A

❐ Maximum standby current: 75 A

to the memory location specified. BHE controls I/O₈through

I/O_15;BLE controls I/O₀through I/O₇.

■ High speed: 45 ns / 55 ns

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on I/O lines (I/O₀through I/O₁₅). Byte

accesses can be performed by asserting the required byte

enable signal (BHE, BLE) to read either the upper byte or the

lower byte of data from the specified address location.

■ Embedded error-correcting code (ECC) for single-bit error

correction

■ Temperature Ranges:

❐ Automotive-A: -40 C to +85 C

❐ Automotive-E: -40 C to +125 C

All I/Os (I/O₀through I/O₁₅) are placed in a HI-Z state when the

device is deselected (CE₁HIGH / CE₂LOW for dual chip-enable

■ Operating voltage range: 2.2 V to 3.6 V

■ 1.0-V data retention

device), or control signals are de-asserted (OE, BLE, and BHE).

These devices also have a unique “Byte Power down” feature

■ TTL-compatible inputs and outputs

where if both the Byte Enables (BHE and BLE) are disabled, the

devices seamlessly switches to standby mode irrespective of the

state of the chip enable(s), thereby saving power.

■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I

packages

The CY62167G device is available in a Pb-free 48-ball VFBGA

and 48-pin TSOP I packages. The device in the 48-pin TSOP I

package can also be configured to function as a 2M words × 8

bit device.The logic block diagram is on page 2. Refer to Pin

Configurations on page 4 and the associated footnotes for

details.

Functional Description

CY62167G is high-performance CMOS low-power (MoBL)

SRAM devices with embedded ECC. This device is offered in

dual chip-enable.

Devices with dual chip-enable are accessed by asserting both

chip-enable inputs – CE₁as LOW and CE₂as HIGH.

Note

1. This device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-84902 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 3, 2017

12 3 4 5 6 7...19

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与CY62167G30-55BVXET相关器件

型号	品牌	获取价格	描述	数据表
CY62167G30-55ZXET	INFINEON	获取价格	Asynchronous SRAM
CY62167G-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167G-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167G-45ZXI	INFINEON	获取价格	Asynchronous SRAM
CY62167G-45ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167G-55BVXE	CYPRESS	获取价格	Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167GE18-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167GE18-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45BV1XI	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45BV1XIT	INFINEON	获取价格	Asynchronous SRAM

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