Datasheet > CY62167GN30-45ZXIT

CY62167GN30-45ZXIT

更新时间： 2024-01-22 18:18:46

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
18页	581K
描述
Asynchronous SRAM

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数据手册

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CY62167GN30 MoBL

16-Mbit (1M × 16/2M × 8) Static RAM

16-Mbit (1M

× 16/2M × 8) Static RAM

More Battery Life™ (MoBL^®) in portable applications such as

cellular telephones. The device also has an automatic power

down feature that reduces power consumption by 99 percent

when addresses are not toggling. Place the device into standby

mode when deselected (CE₁HIGH or CE₂LOW or both BHE and

Features

■ Ultra-low standby power

❐ Typical standby current: 1.5 A

❐ Maximum standby current: 8 A

BLE are HIGH). The input and output pins (I/O₀through I/O₁₅

)

■ TSOP I package configurable as 1M × 16 or 2M × 8 SRAM

are placed in a high impedance state when: the device is

deselected (CE₁HIGH or CE₂LOW), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH), or a write operation is in progress (CE₁LOW,

CE₂HIGH and WE LOW).

■ Very high speed: 45 ns

■ Temperature ranges

❐ Industrial: –40 °C to +85 °C

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇) is

written into the location specified on the address pins (A₀through

■ Wide voltage range: 2.2 V to 3.6 V

■ Easy memory expansion with CE₁, CE₂, and OE Features

■ Automatic power-down when deselected

A₁₉). If Byte High Enable (BHE) is LOW, then data from the I/O

pins (I/O₈through I/O₁₅) is written into the location specified on

the address pins (A₀through A₁₉).

■ CMOS for optimum speed and power

■ Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See Truth Table on page 12

for a complete description of read and write modes.

Functional Description

The CY62167GN30 is a high performance CMOS static RAM

organized as 1M words by 16 bits or 2M words by 8 bits. This

device features an advanced circuit design that provides an ultra

low active current. Ultra low active current is ideal for providing

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

1M × 16/2M × 8

RAM Array

I/O₀–I/O₇

A ₄

I/O₈–I/O₁₅

A ₃

A ₂

A ₁

A ₀

COLUMN DECODER

BYTE

BHE

CE₂

PowerDown

Circuit

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 002-28515 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 16, 2020

12 3 4 5 6 7...18

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与CY62167GN30-45ZXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62167GN-45ZXI	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62167GN-45ZXIT	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62168DV3_06	CYPRESS	获取价格	16-Mbit (2M x 8) MoBL㈢ Static RAM
CY62168DV30	CYPRESS	获取价格	16-Mbit (2048K x 8) Static RAM
CY62168DV30_09	CYPRESS	获取价格	16-Mbit (2M x 8) MoBL Static RAM
CY62168DV30_10	CYPRESS	获取价格	16-Mbit (2M x 8) MoBL? Static RAM
CY62168DV30L-55BVI	CYPRESS	获取价格	Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48
CY62168DV30L-55BVXI	CYPRESS	获取价格	16-Mbit (2048K x 8) Static RAM
CY62168DV30L-70BVI	CYPRESS	获取价格	Standard SRAM, 2MX8, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48
CY62168DV30L-70BVXI	CYPRESS	获取价格	16-Mbit (2048K x 8) Static RAM

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