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CY62167GN18-55BVXI

更新时间： 2024-01-24 22:41:50
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 532K
描述
16-Mbit (1M × 16/2M × 8) Static RAM

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CY62167GN18-55BVXI 数据手册

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CY62167GN MoBL®  
16-Mbit (1M × 16/2M × 8) Static RAM  
16-Mbit (1M  
× 16/2M × 8) Static RAM  
Features  
Functional Description  
■ Ultra-low standby power  
❐ Typical standby current: 5.5 A  
❐ Maximum standby current: 16 A  
The CY62167GN is a high performance CMOS static RAM  
organized as 1M words by 16 bits or 2M words by 8 bits. This  
device features an advanced circuit design that provides an ultra  
low active current. Ultra low active current is ideal for providing  
More Battery Life(MoBL®) in portable applications such as  
cellular telephones. The device also has an automatic power  
down feature that reduces power consumption by 99 percent  
when addresses are not toggling. Place the device into standby  
mode when deselected (CE1 HIGH or CE2 LOW or both BHE and  
■ TSOP I package configurable as 1M × 16 or 2M × 8 SRAM  
■ Very high speed: 45 ns  
■ Temperature ranges  
❐ Industrial: –40 °C to +85 °C  
BLE are HIGH). The input and output pins (I/O0 through I/O15  
)
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V  
to 5.5 V  
are placed in a high impedance state when: the device is  
deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH), or a write operation is in progress (CE1 LOW,  
CE2 HIGH and WE LOW).  
■ Easy memory expansion with CE1, CE2, and OE Features  
■ Automatic power-down when deselected  
■ CMOS for optimum speed and power  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is  
written into the location specified on the address pins (A0 through  
A19). If Byte High Enable (BHE) is LOW, then data from the I/O  
pins (I/O8 through I/O15) is written into the location specified on  
the address pins (A0 through A19).  
■ Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See Truth Table on page 13  
for a complete description of read and write modes.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
1M × 16/2M × 8  
RAM Array  
I/O0–I/O7  
A 4  
I/O8–I/O15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE  
CE2  
1
PowerDown  
Circuit  
CE  
1
OE  
BHE  
BLE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-93628 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 23, 2017  
1234567...19

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