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CY62168DV30L-55BVI PDF预览

CY62168DV30L-55BVI

更新时间: 2024-11-18 21:12:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
9页 228K
描述
Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48

CY62168DV30L-55BVI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.85最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B48
JESD-609代码:e0长度:9.5 mm
内存密度:16777216 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:48字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1 mm
最大待机电流:0.000015 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.03 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:8 mm
Base Number Matches:1

CY62168DV30L-55BVI 数据手册

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CY62168DV30  
MoBL  
16-Mbit (2048K x 8) Static RAM  
addresses are not toggling. The device can be put into standby  
mode reducing power consumption by more than 99% when  
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)  
LOW. The input/output pins (I/O0 through I/O7) are placed in  
a high-impedance state when: deselected Chip Enable 1  
(CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled  
(OE HIGH), or during a write operation (Chip Enable 1 (CE1)  
LOW and Chip Enable 2 (CE2) HIGH and WE LOW).  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable  
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address  
pins(A0 through A20).  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW and Chip  
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW). See the truth table for a complete description of read  
and write modes.  
Features  
• Very high speed: 55 ns and 70 ns  
— Wide voltage range: 2.20V – 3.60V  
• Ultra-low active power  
— Typical active current: 2 mA @ f = 1 MHz  
— Typical active current: 15 mA @ f = fmax  
• Ultra-low standby power  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball FBGA  
Functional Description[1]  
The CY62168DV30 is a high-performance CMOS static RAMs  
organized as 2048Kbit words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can be put into  
standby mode reducing power consumption by 90% when  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
Data in Drivers  
A0  
A1  
A2  
A3  
A4  
1
2
A
A5  
A6  
3
4
5
2048K x 8  
A7  
ARRAY  
A98  
A10  
A11  
A12  
6
7
POWER  
DOWN  
COLUMN  
CE  
CE  
1
2
DECODER  
I/O  
WE  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05329 Rev. *D  
Revised September 14, 2004  

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