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CY62168DV30L-55BVXI PDF预览

CY62168DV30L-55BVXI

更新时间: 2024-11-17 22:24:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 232K
描述
16-Mbit (2048K x 8) Static RAM

CY62168DV30L-55BVXI 数据手册

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CY62168DV30  
MoBL  
16-Mbit (2048K x 8) Static RAM  
addresses are not toggling. The device can be put into standby  
mode reducing power consumption by more than 99% when  
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)  
LOW. The input/output pins (I/O0 through I/O7) are placed in  
a high-impedance state when: deselected Chip Enable 1  
(CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled  
(OE HIGH), or during a write operation (Chip Enable 1 (CE1)  
LOW and Chip Enable 2 (CE2) HIGH and WE LOW).  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable  
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address  
pins(A0 through A20).  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW and Chip  
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW). See the truth table for a complete description of read  
and write modes.  
Features  
• Very high speed: 55 ns and 70 ns  
— Wide voltage range: 2.20V – 3.60V  
• Ultra-low active power  
— Typical active current: 2 mA @ f = 1 MHz  
— Typical active current: 15 mA @ f = fmax  
• Ultra-low standby power  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball FBGA  
Functional Description[1]  
The CY62168DV30 is a high-performance CMOS static RAMs  
organized as 2048Kbit words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can be put into  
standby mode reducing power consumption by 90% when  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
Data in Drivers  
A0  
A1  
A2  
A3  
A4  
1
2
A
A5  
A6  
3
4
5
2048K x 8  
A7  
ARRAY  
A98  
A10  
A11  
A12  
6
7
POWER  
DOWN  
COLUMN  
CE  
CE  
1
2
DECODER  
I/O  
WE  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05329 Rev. *D  
Revised September 14, 2004  

CY62168DV30L-55BVXI 替代型号

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