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CY62168DV30LL-55BVIT PDF预览

CY62168DV30LL-55BVIT

更新时间： 2024-11-05 21:12:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
15页 378K
描述
Standard SRAM, 2MX8, 55ns, CMOS, PBGA48

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CY62168DV30LL-55BVIT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：ObsoleteReach Compliance Code：compliant
风险等级：5.91最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
内存密度：16777216 bit内存集成电路类型：STANDARD SRAM
内存宽度：8端子数量：48
字数：2097152 words字数代码：2000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, FINE PITCH
并行/串行：PARALLEL电源：2.5/3.3 V
认证状态：Not Qualified最大待机电流：0.00001 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.03 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOMBase Number Matches：1

CY62168DV30LL-55BVIT 数据手册

 浏览型号CY62168DV30LL-55BVIT的Datasheet PDF文件第2页浏览型号CY62168DV30LL-55BVIT的Datasheet PDF文件第3页浏览型号CY62168DV30LL-55BVIT的Datasheet PDF文件第4页浏览型号CY62168DV30LL-55BVIT的Datasheet PDF文件第5页浏览型号CY62168DV30LL-55BVIT的Datasheet PDF文件第6页浏览型号CY62168DV30LL-55BVIT的Datasheet PDF文件第7页 
CY62168DV30 MoBL®  
16-Mbit (2 M × 8) Static RAM  
16-Mbit (2  
M × 8) Static RAM  
consumption. The device can be put into standby mode reducing  
power consumption by 90% when addresses are not toggling.  
The device can be put into standby mode reducing power  
consumption by more than 99% when deselected Chip Enable 1  
(CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins  
(I/O0 through I/O7) are placed in a high-impedance state when:  
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)  
LOW, outputs are disabled (OE HIGH), or during a write  
operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2)  
HIGH and WE LOW).  
Features  
■ Very high speed  
❐ 55 ns  
■ Wide voltage range  
❐ 2.2 V–3.6 V  
■ Ultra-low active power  
❐ Typical active current: 2 mA at f = 1 MHz  
❐ Typical active current: 15 mA at f = fMax (55 ns Speed)  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable  
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins(A0  
through A20).  
■ Ultra-low standby power  
■ Easy memory expansion with CE1, CE2 and OE features  
■ Automatic power-down when deselected  
Reading from the device is accomplished by taking Chip Enable  
1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2)  
HIGH while forcing Write Enable (WE) HIGH. Under these  
conditions, the contents of the memory location specified by the  
address pins appear on the I/O pins.  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed/power  
■ Available in non Pb-free 48-ball very fine ball grid array  
(VFBGA) package.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1 LOW  
and CE2 HIGH), the outputs are disabled (OE HIGH), or during  
a write operation (CE1 LOW and CE2 HIGH and WE LOW). See  
the Truth Table on page 10 for a complete description of read and  
write modes.  
Functional Description  
The CY62168DV30 is a high-performance CMOS static RAMs  
organized as 2048Kbit words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life(MoBL) in portable  
applications such as cellular telephones. The device also has an  
automatic power-down feature that significantly reduces power  
For a complete list of related documentation, click here.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
Data in Drivers  
A0  
A1  
A2  
A3  
A4  
A
1
2
A56  
3
4
5
2048K x 8  
ARRAY  
A
A7  
A98  
A10  
A11  
A12  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
CE  
1
2
I/O  
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 38-05329 Rev. *M  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 3, 2015  
 
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CY62168DV30LL-55BVIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62168DV30LL-55BVI CYPRESS

完全替代

 16-Mbit (2M x 8) MoBL㈢ Static RAM

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