Datasheet > CY62168EV30_11

CY62168EV30_11

更新时间： 2024-11-05 09:42:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	852K
描述
16-Mbit (2 M x 8) Static RAM Automatic power-down when deselected

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CY62168EV30_11 数据手册

CY62168EV30 MoBL^®

16-Mbit (2 M × 8) Static RAM

16-Mbit (2

M × 8) Static RAM

automatic power-down feature that significantly reduces power

consumption by 90% when addresses are not toggling. Placing

the device into standby mode reduces power consumption by

more than 99% when deselected (Chip Enable 1 (CE₁) HIGH or

Chip Enable 2 (CE₂) LOW). The input and output pins (I/O₀

through I/O₇) are placed in a high impedance state when: the

Features

■ Very high speed: 45 ns

■ Wide voltage range: 2.20 V to 3.60 V

■ Ultra low standby power

❐ Typical standby current: 1.5 µA

❐ Maximum standby current: 12 µA

device is deselected (Chip Enable

1 (CE₁) HIGH or

Chip Enable 2 (CE₂) LOW), outputs are disabled (OE HIGH), or

a write operation is in progress (Chip Enable 1 (CE₁) LOW and

Chip Enable 2 (CE₂) HIGH and WE LOW).

■ Ultra low active power

❐ Typical active current: 2.2 mA at f = 1 MHz

Write to the device by taking Chip Enable 1 (CE₁) LOW and

Chip Enable 2 (CE₂) HIGH and the Write Enable (WE) input

LOW. Data on the eight I/O pins (I/O₀through I/O₇) is then written

into the location specified on the address pins (A₀through A₂₀).

■ Easy memory expansion with CE₁, CE₂and OE features

■ Automatic power-down when deselected

■ CMOS for optimum speed/power

Read from the device by taking Chip Enable 1 (CE₁) and

Output Enable (OE) LOW and Chip Enable 2 (CE₂) HIGH while

forcing Write Enable (WE) HIGH. Under these conditions, the

contents of the memory location specified by the address pins

will appear on the I/O pins.

■ Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin

TSOP I package, refer to CY62167EV30 datasheet.

Functional Description

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or a

write operation is in progress (CE₁LOW and CE₂HIGH and WE

LOW). See the Truth Table on page 11 for a complete description

of read and write modes.

The CY62168EV30 is a high performance CMOS static RAM

organized as 2 M words by 8-bits. This device features advanced

circuit design to provide an ultra low active current. This is ideal

for providing More Battery Life (MoBL^) in portable

applications such as cellular telephones. The device also has an

Logic Block Diagram

I/O

DATA IN DRIVERS

I/O

2M x 8

I/O

ARRAY

POWER

DOWN

COLUMN DECODER

Cypress Semiconductor Corporation

Document #: 001-07721 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 10, 2011

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与CY62168EV30_11相关器件

型号	品牌	获取价格	描述	数据表
CY62168EV30LL-45BVXI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62168EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62168EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62168G	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bits) Static RAM with
CY62168G18-55BVXI	CYPRESS	获取价格	Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62168G18-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62168G18-55BVXIT	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bits) Static RAM with
CY62168G18-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62168G30-45BVXI	CYPRESS	获取价格	16-Mbit (2M words Ã 8 bits) Static RAM with
CY62168G30-45BVXI	INFINEON	获取价格	Asynchronous SRAM

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