Datasheet > CY62168DV30_10

CY62168DV30_10

更新时间： 2024-02-20 04:55:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	480K
描述
16-Mbit (2M x 8) MoBL? Static RAM

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CY62168DV30_10 数据手册

CY62168DV30 MoBL^®

16-Mbit (2M x 8) MoBL^®Static RAM

automatic power-down feature that significantly reduces power

consumption. The device can be put into standby mode reducing

power consumption by 90% when addresses are not toggling.

The device can be put into standby mode reducing power

consumption by more than 99% when deselected Chip Enable 1

(CE₁) HIGH or Chip Enable 2 (CE₂) LOW. The input/output pins

(I/O₀through I/O₇) are placed in a high-impedance state when:

deselected Chip Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂)

LOW, outputs are disabled (OE HIGH), or during a write

operation (Chip Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂)

HIGH and WE LOW).

Features

■ Very high speed

❐ 55 ns

■ Wide voltage range

❐ 2.2 V – 3.6 V

■ Ultra-low active power

❐ Typical active current: 2 mA @ f = 1 MHz

❐ Typical active current: 15 mA @ f = f_Max(55 ns Speed)

■ Ultra-low standby power

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) LOW and Chip Enable 2 (CE₂) HIGH and Write Enable

(WE) input LOW. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins(A₀

through A₂₀).

■ Easy memory expansion with CE₁, CE₂and OE features

■ Automatic power-down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

Reading from the device is accomplished by taking Chip Enable

1 (CE₁) and Output Enable (OE) LOW and Chip Enable 2 (CE₂)

HIGH while forcing Write Enable (WE) HIGH. Under these

conditions, the contents of the memory location specified by the

address pins will appear on the I/O pins.

optimum speed/power

■ Available in non Pb-free 48-ball very fine ball grid array

(VFBGA) package.

Functional Description^[1]

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁LOW

and CE₂HIGH), the outputs are disabled (OE HIGH), or during

a write operation (CE₁LOW and CE₂HIGH and WE LOW). See

the “Truth Table” on page 10 for a complete description of read

and write modes.

The CY62168DV30 is a high-performance CMOS static RAMs

organized as 2048Kbit words by 8 bits. This device features

advanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

Logic Block Diagram

I/O

Data in Drivers

A₀

A₁

A₂

A₃

A₄

A₅

A₆

2048K x 8

ARRAY

A⁷

A₉⁸

A₁₀

A₁₁

A₁₂

POWER

DOWN

COLUMN

DECODER

I/O

Note

1. For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.

Cypress Semiconductor Corporation

Document Number : 38-05329 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 19, 2010

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与CY62168DV30_10相关器件

型号	品牌	获取价格	描述	数据表
CY62168DV30L-55BVI	CYPRESS	获取价格	Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48
CY62168DV30L-55BVXI	CYPRESS	获取价格	16-Mbit (2048K x 8) Static RAM
CY62168DV30L-70BVI	CYPRESS	获取价格	Standard SRAM, 2MX8, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48
CY62168DV30L-70BVXI	CYPRESS	获取价格	16-Mbit (2048K x 8) Static RAM
CY62168DV30LL	CYPRESS	获取价格	16-Mbit (2M x 8) MoBL? Static RAM
CY62168DV30LL-55BVI	CYPRESS	获取价格	16-Mbit (2M x 8) MoBL㈢ Static RAM
CY62168DV30LL-55BVIT	CYPRESS	获取价格	Standard SRAM, 2MX8, 55ns, CMOS, PBGA48
CY62168DV30LL-55BVXI	CYPRESS	获取价格	16-Mbit (2048K x 8) Static RAM
CY62168DV30LL-55BVXIT	CYPRESS	获取价格	Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM PITCH, LEAD FREE, VFBGA-48
CY62168DV30LL-70BVI	CYPRESS	获取价格	Standard SRAM, 2MX8, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48

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