Datasheet > CY62167G-55BVXE

CY62167G-55BVXE

更新时间： 2024-11-18 21:21:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
19页	321K
描述
Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

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CY62167G-55BVXE 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	VFBGA,	Reach Compliance Code：	compliant
风险等级：	5.71	最长访问时间：	55 ns
JESD-30 代码：	R-PBGA-B48	长度：	8 mm
内存密度：	16777216 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	16	功能数量：	1
端子数量：	48	字数：	1048576 words
字数代码：	1000000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	1MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	并行/串行：	PARALLEL
座面最大高度：	1 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子形式：	BALL
端子节距：	0.75 mm	端子位置：	BOTTOM
宽度：	6 mm	Base Number Matches：	1

CY62167G-55BVXE 数据手册

CY62167G

PRELIMINARY

CY62167GE Automotive

16-Mbit (1 M words × 16 bit) Static RAM with

Error-Correcting Code (ECC)

16-Mbit (1

M words × 16 bit) Static RAM with Error-Correcting Code (ECC)

Data writes are performed by asserting the Write Enable input

(WE LOW), and providing the data and address on device data

(I/O₀through I/O₁₅) and address (A₀through A₁₉) pins

respectively. The Byte High/Low Enable (BHE, BLE) inputs

control byte writes, and write data on the corresponding I/O lines

to the memory location specified. BHE controls I/O₈through

I/O₁₅and BLE controls I/O₀through I/O₇.

Features

■ Ultra-low standby power

❐ Typical standby current: 3.2 A

❐ Maximum standby current: 60 A

■ High speed: 55 ns

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on I/O lines (I/O₀through I/O₁₅). Byte

accesses can be performed by asserting the required byte

enable signal (BHE, BLE) to read either the upper byte or the

lower byte of data from the specified address location.

■ Embedded error-correcting code (ECC) for single-bit error

correction

■ Wide voltage range: 1.65V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V

■ 1.0-V data retention

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ ERR pin to indicate 1-bit error detection and correction

■ Available in Pb-free 48-ball VFBGA package

All I/Os (I/O₀through I/O₁₅) are placed in a high impedance state

when the device is deselected (CE HIGH for single chip enable

device and CE₁HIGH / CE₂LOW for dual chip enable device),

or control signals are de-asserted (OE, BLE, BHE).

These devices also have a unique “Byte Power down” feature,

where, if both the Byte Enables (BHE and BLE) are disabled, the

devices seamlessly switch to standby mode irrespective of the

state of the chip enable(s), thereby saving power.

Functional Description

CY62167G and CY62167GE are high-performance CMOS

low-power (MoBL) SRAM devices with embedded ECC. Both

devices are offered in single and dual chip enable options and in

multiple pin configurations. The CY62167GE device includes an

error indication pin that signals an error-detection and correction

event during a read cycle.

On the CY62167GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = High)^[1]. See the Truth Table

– CY62167G on page 14 for a complete description of read and

write modes.

Devices with a single chip enable input are accessed by

asserting the chip enable input (CE) LOW. Dual chip enable

devices are accessed by asserting both chip enable inputs – CE₁

as LOW and CE₂as HIGH.

The CY62167G and CY62167GE devices are available in a

Pb-free 48-ball VFBGA package. The logic block diagrams are

on page 2. Refer to the Pin Configurations section and the

associated footnotes for details.

Note

1. This device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-84902 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 16, 2013

12 3 4 5 6 7...19

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与CY62167G-55BVXE相关器件

型号	品牌	获取价格	描述	数据表
CY62167GE18-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167GE18-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45BV1XI	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45BV1XIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45ZXI	CYPRESS	获取价格	Standard SRAM, 1MX16, 45ns, CMOS, PDSO48, TSOP1-48
CY62167GE30-45ZXI	INFINEON	获取价格	Asynchronous SRAM
CY62167GE30-45ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GE-45ZXI	INFINEON	获取价格	Asynchronous SRAM

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