Datasheet > CY62167GN

CY62167GN

更新时间： 2024-11-22 00:54:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	532K
描述
16-Mbit (1M Ã 16/2M Ã 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62167GN 数据手册

CY62167GN MoBL^®

16-Mbit (1M × 16/2M × 8) Static RAM

16-Mbit (1M

× 16/2M × 8) Static RAM

Features

Functional Description

■ Ultra-low standby power

❐ Typical standby current: 5.5 A

❐ Maximum standby current: 16 A

The CY62167GN is a high performance CMOS static RAM

organized as 1M words by 16 bits or 2M words by 8 bits. This

device features an advanced circuit design that provides an ultra

low active current. Ultra low active current is ideal for providing

More Battery Life (MoBL^®) in portable applications such as

cellular telephones. The device also has an automatic power

down feature that reduces power consumption by 99 percent

when addresses are not toggling. Place the device into standby

mode when deselected (CE₁HIGH or CE₂LOW or both BHE and

■ TSOP I package configurable as 1M × 16 or 2M × 8 SRAM

■ Very high speed: 45 ns

■ Temperature ranges

❐ Industrial: –40 °C to +85 °C

BLE are HIGH). The input and output pins (I/O₀through I/O₁₅

)

■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V

to 5.5 V

are placed in a high impedance state when: the device is

deselected (CE₁HIGH or CE₂LOW), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH), or a write operation is in progress (CE₁LOW,

CE₂HIGH and WE LOW).

■ Easy memory expansion with CE₁, CE₂, and OE Features

■ Automatic power-down when deselected

■ CMOS for optimum speed and power

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇) is

written into the location specified on the address pins (A₀through

A₁₉). If Byte High Enable (BHE) is LOW, then data from the I/O

pins (I/O₈through I/O₁₅) is written into the location specified on

the address pins (A₀through A₁₉).

■ Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See Truth Table on page 13

for a complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

1M × 16/2M × 8

RAM Array

I/O₀–I/O₇

A ₄

I/O₈–I/O₁₅

A ₃

A ₂

A ₁

A ₀

COLUMN DECODER

BYTE

BHE

CE₂

PowerDown

Circuit

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-93628 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 23, 2017

12 3 4 5 6 7...19

中文翻译

下载PDF

与CY62167GN相关器件

型号	品牌	获取价格	描述	数据表
CY62167GN18-55BVXI	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62167GN18-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167GN18-55BVXIT	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62167GN18-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GN30-45BVXI	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62167GN30-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167GN30-45BVXIT	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62167GN30-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167GN30-45ZXI	CYPRESS	获取价格	16-Mbit (1M Ã 16/2M Ã 8) Static RAM
CY62167GN30-45ZXI	INFINEON	获取价格	Asynchronous SRAM

与CY62167GN相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

31
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

22
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

51
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

50

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62167GN

CY62167GN 数据手册

与CY62167GN相关器件

与CY62167GN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62167GN

CY62167GN 数据手册

与CY62167GN相关器件

与CY62167GN相关文章

您还可以找

您在本页遇到什么问题？