CY62167G30/CY62167GE30
16-Mbit (1M words × 16-bit/
2M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
CY62167G30/CY62167GE30, 16-Mbit (1M words
× 16-bit/2M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
Features
■ Ultra-low standby current
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 8 µA
■ High speed: 45 ns
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. You can
access read data on the I/O lines (I/O0 through I/O15). To perform
byte accesses, assert the required byte enable signal (BHE or
BLE) to read either the upper byte or the lower byte of data from
the specified address location.
■ Embedded error-correcting code (ECC) for single-bit error
correction[1]
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.0-V data retention
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE1 HIGH/CE2 LOW for a dual chip enable device),
or the control signals are de-asserted (OE, BLE, BHE).
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ 48-pin TSOP I package configurable as 1M 16 or 2M 8
These devices have a unique Byte Power-down feature where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to the standby mode irrespective of
the state of the chip enables, thereby saving power.
SRAM
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
On the CY62167GE30 devices, the detection and correction of
a single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
– CY62167G30/CY62167GE30 on page 15 for a complete
description of read and write modes.
Functional Description
CY62167G30 and CY62167GE30 are high-performance CMOS,
low-power (MoBL®) SRAM devices with embedded ECC[2]. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62167GE30 device includes
an ERR pin that signals a single-bit error-detection and
correction event during a read cycle.
The CY62167G30 and CY62167GE30 devices are available in
a Pb-free 48-pin TSOP I package and 48-ball VFBGA packages.
See the Logic Block Diagram – CY62167G30 on page 2.
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
The device in the 48-pin TSOP I package can also be configured
to function as a 2M words 8 bit device. Refer to the Pin
Configurations section for details.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
For a complete list of related documentation, click here.
Product Portfolio
Current Consumption
Features and
Options
(see the Pin
Configurations
section)
Operating ICC, (mA) Standby, ISB2 (µA)
Product
Range
VCC Range (V) Speed (ns)
f = fmax
Typ[5]
Max
Typ[5]
Max
CY62167G30/
Single or Dual Chip Industrial
2.2 V–3.6 V
45
29
35
1.5
8
CY62167GE30[3, 4] Enables Optional
ERR pin
Notes
1. SER FIT rate <0.1 FIT/Mb. Refer to AN88889 for details.
2. This device does not support automatic write-back on error detection.
3. This device offers improved I , I
and I
specifications compared to the previous revision with same marketing part number.
CC SB1
SB2
4. For previous version of this device, kindly refer here. Further details about improvement and comparison between old and new versions can be found in the PIN193805.
5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.
CC
CC
A
Cypress Semiconductor Corporation
Document Number: 002-20054 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 18, 2020
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