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CY62167EV18LL-55BAXI PDF预览

CY62167EV18LL-55BAXI

更新时间： 2024-11-20 03:08:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器
页数 文件大小 规格书
12页 532K
描述
16-Mbit (1M x 16) Static RAM

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中文翻译

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CY62167EV18LL-55BAXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：6 X 7 MM, 1 MM HEIGHT, LEAD FREE, MO-216, VFBGA-48
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.36最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：7 mm
内存密度：16777216 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL电源：1.8/2 V
认证状态：Not Qualified座面最大高度：1.17 mm
最大待机电流：0.00001 A最小待机电流：1 V
子类别：SRAMs最大压摆率：0.03 mA
最大供电电压 (Vsup)：2.25 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

CY62167EV18LL-55BAXI 数据手册

 浏览型号CY62167EV18LL-55BAXI的Datasheet PDF文件第2页浏览型号CY62167EV18LL-55BAXI的Datasheet PDF文件第3页浏览型号CY62167EV18LL-55BAXI的Datasheet PDF文件第4页浏览型号CY62167EV18LL-55BAXI的Datasheet PDF文件第5页浏览型号CY62167EV18LL-55BAXI的Datasheet PDF文件第6页浏览型号CY62167EV18LL-55BAXI的Datasheet PDF文件第7页 
CY62167EV18 MoBL®  
16-Mbit (1M x 16) Static RAM  
by 99% when addresses are not toggling. Place the device into  
standby mode when deselected (CE1 HIGH or CE2 LOW or both  
BHE and BLE are HIGH). The input and output pins (IO0 through  
IO15) are placed in a high impedance state when: the device is  
deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE  
HIGH); both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH); and a write operation is in progress (CE1  
LOW, CE2 HIGH and WE LOW).  
Features  
■ Very high speed: 55 ns  
■ Wide voltage range: 1.65V – 2.25V  
■ Ultra low standby power  
❐ Typical standby current: 1.5 µA  
❐ Maximum standby current: 12 µA  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written  
into the location specified on the address pins (A0 through A19).  
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8  
through IO15) is written into the location specified on the address  
pins (A0 through A19).  
■ Ultra low active power  
❐ Typical active current: 2.2 mA @ f = 1 MHz  
■ Easy memory expansion with CE1, CE2, and OE features  
■ Automatic power down when deselected  
■ CMOS for optimum speed and power  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO8 to IO15. See the Truth Table on page 9  
for a complete description of read and write modes.  
■ Offered in Pb-free 48-ball VFBGA packages  
Functional Description  
The CY62167EV18 is a high performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that reduces power consumption  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
1M × 16  
RAM ARRAY  
IO0–IO7  
IO8–IO15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE2  
CE  
1
PowerDown  
Circuit  
CE  
1
OE  
BHE  
BLE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05447 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 16, 2007  
1234567...12

中文翻译

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CY62167EV18LL-55BAXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62167EV18LL-55BVXIT CYPRESS

完全替代

 Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV18LL-55BVI CYPRESS

完全替代

 16 Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVXI CYPRESS

完全替代

 16-Mbit (1M x 16) Static RAM

与CY62167EV18LL-55BAXI相关器件

型号 品牌 获取价格 描述 数据表
CY62167EV18LL-55BVI CYPRESS

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 		16 Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVI INFINEON

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 		Asynchronous SRAM
CY62167EV18LL-55BVIT INFINEON

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 		Asynchronous SRAM
CY62167EV18LL-55BVXI CYPRESS

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 		16-Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVXI INFINEON

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 		Asynchronous SRAM
CY62167EV18LL-55BVXIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV18LL-55BVXIT INFINEON

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 		Asynchronous SRAM
CY62167EV30 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30_09 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167EV30_10 CYPRESS

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 		16-Mbit (1M x 16 / 2M x 8) Static RAM

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