Datasheet > CY62167EV18_11

CY62167EV18_11

更新时间： 2024-11-20 12:50:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	314K
描述
16 Mbit (1M x 16) Static RAM Automatic power down when deselected

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CY62167EV18_11 数据手册

CY62167EV18 MoBL^®

16 Mbit (1M x 16) Static RAM

16 Mbit (1M

x 16) Static RAM

automatic power down feature that reduces power consumption

by 99 percent when addresses are not toggling. Place the device

into standby mode when deselected (CE₁HIGH or CE₂LOW or

both BHE and BLE are HIGH). The input and output pins (I/O₀

through I/O₁₅) are placed in a high impedance state when: the

device is deselected (CE₁HIGH or CE₂LOW); outputs are

disabled (OE HIGH); both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH); and a write operation is

in progress (CE₁LOW, CE₂HIGH and WE LOW).

Features

■ Very high speed: 55 ns

■ Wide voltage range: 1.65 V to 2.25 V

■ Ultra low standby power

❐ Typical standby current: 1.5 A

❐ Maximum standby current: 12 A

■ Ultra low active power

❐ Typical active current: 2.2 mA at f = 1 MHz

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇) is

written into the location specified on the address pins (A₀through

A₁₉). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O₈through I/O₁₅) is written into the location specified on the

address pins (A₀through A₁₉).

■ Easy memory expansion with CE₁, CE₂, and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Offered in Pb-free 48-ball very fine ball grid array (VFBGA)

packages

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See the Truth Table on page

10 for a complete description of read and write modes.

Functional Description

The CY62167EV18 is a high performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life (MoBL^®) in portable

applications such as cellular telephones. The device also has an

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

1M × 16

RAM ARRAY

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₃

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

PowerDown

Circuit

BHE

BLE

Cypress Semiconductor Corporation

Document #: 38-05447 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 29, 2011

12 3 4 5 6 7...16

中文翻译

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与CY62167EV18_11相关器件

型号	品牌	获取价格	描述	数据表
CY62167EV18LL-45BVXI	CYPRESS	获取价格	Standard SRAM, 1MX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV18LL-55BAXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVI	CYPRESS	获取价格	16 Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVI	INFINEON	获取价格	Asynchronous SRAM
CY62167EV18LL-55BVIT	INFINEON	获取价格	Asynchronous SRAM
CY62167EV18LL-55BVXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167EV18LL-55BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62167EV18LL-55BVXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62167EV18LL-55BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167EV30	CYPRESS	获取价格	16-Mbit (1M x 16 / 2M x 8) Static RAM

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