Datasheet > CY62167DV30LL-70BVXIT

CY62167DV30LL-70BVXIT

更新时间： 2024-11-25 04:17:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	202K
描述
Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

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CY62167DV30

MoBL^®

16-Mbit (1M x 16) Static RAM

also has an automatic power-down feature that significantly

reduces power consumption by 99% when addresses are not

toggling. The device can also be put into standby mode when

deselected (CE₁HIGH or CE₂LOW or both BHE and BLE are

HIGH). The input/output pins (I/O₀through I/O₁₅) are placed

in a high-impedance state when: deselected (CE₁HIGH or CE₂

LOW), outputs are disabled (OE HIGH), both Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

or during a Write operation (CE₁LOW, CE₂HIGH and WE

LOW).

Features

• Very high speed: 45 ns

• Wide voltage range: 2.20V – 3.60V

• Ultra-low active power

— Typical active current: 2 mA @ f = 1 MHz

— Typical active current: 18.5 mA @ f = f_max(45 ns

speed)

• Ultra-low standby power

Writing to the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Write Enable (WE) input LOW.

If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀

through I/O₇), is written into the location specified on the

address pins (A₀through A₁₉). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written into

the location specified on the address pins (A₀through A₁₉).

• Easy memory expansion with CE₁, CE₂, and OE

features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered in a 48-ball BGA and 48-pin TSOPI

Reading from the device is accomplished by taking Chip

Enables (CE₁LOW and CE₂HIGH) and Output Enable (OE)

LOW while forcing the Write Enable (WE) HIGH. If Byte Low

Enable (BLE) is LOW, then data from the memory location

specified by the address pins will appear on I/O₀to I/O₇. If Byte

High Enable (BHE) is LOW, then data from memory will appear

on I/O₈to I/O₁₅. See the truth table at the back of this data

sheet for a complete description of Read and Write modes.

Functional Description^[1]

The CY62167DV30 is a high-performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

1M × 16

RAM Array

I/O0 – I/O7

I/O8 – I/O15

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

BLE

Power-down

Circuit

CE₂

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05328 Rev. *F

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised December 20, 2004

12 3 4 5 6 7...12

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与CY62167DV30LL-70BVXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62167DV30LL-70ZI	ROCHESTER	获取价格	1MX16 STANDARD SRAM, 70ns, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48
CY62167DV30LL-70ZI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167DV30LL-70ZIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48
CY62167DV30LL-70ZXI	ROCHESTER	获取价格	1MX16 STANDARD SRAM, 70ns, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-48
CY62167DV30LL-70ZXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-48
CY62167E	CYPRESS	获取价格	16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167E_09	CYPRESS	获取价格	16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167E_10	CYPRESS	获取价格	16-Mbit (1 M × 16 / 2 M × 8) Static RAM
CY62167E_11	CYPRESS	获取价格	16-Mbit (1 M x 16 / 2 M x 8) Static RAM Automatic power-down when deselected
CY62167E_13	CYPRESS	获取价格	16-Mbit (1 M x 16 / 2 M x 8) Static RAM

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