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CY62167ELL-45ZXI PDF预览

CY62167ELL-45ZXI

更新时间： 2024-11-20 03:54:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 527K
描述
16-Mbit (1M x 16 / 2M x 8) Static RAM

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CY62167ELL-45ZXI 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSOP1包装说明：TSOP1, TSSOP48,.8,20
针数：48Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：2.23
最长访问时间：45 ns备用内存宽度：8
I/O 类型：COMMONJESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：18.4 mm
内存密度：16777216 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1封装等效代码：TSSOP48,.8,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.2 mm最小待机电流：2 V
子类别：SRAMs最大压摆率：0.03 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：12 mm
Base Number Matches：1

CY62167ELL-45ZXI 数据手册

 浏览型号CY62167ELL-45ZXI的Datasheet PDF文件第2页浏览型号CY62167ELL-45ZXI的Datasheet PDF文件第3页浏览型号CY62167ELL-45ZXI的Datasheet PDF文件第4页浏览型号CY62167ELL-45ZXI的Datasheet PDF文件第5页浏览型号CY62167ELL-45ZXI的Datasheet PDF文件第6页浏览型号CY62167ELL-45ZXI的Datasheet PDF文件第7页 
CY62167E MoBL®  
16-Mbit (1M x 16 / 2M x 8) Static RAM  
(CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH).  
The input and output pins (IO0 through IO15) are placed in a  
high impedance state when:  
Features  
• Configurable as 1M x 16 or as 2M x 8 SRAM  
• Very high speed: 45 ns  
• The device is deselected (CE1 HIGH or CE2 LOW)  
• Outputs are disabled (OE HIGH)  
• Wide voltage range: 4.5V–5.5V  
• Ultra low standby power  
• Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH) or  
— Typical standby current: 1.5 µA  
— Maximum standby current: 12 µA  
• Ultra low active power  
• A write operation is in progress (CE1 LOW, CE2 HIGH, and  
WE LOW)  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
— Typical active current: 2.2 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed and power  
• Offered in 48-pin TSOP I package  
(BLE) is LOW, then data from IO pins (IO0 through IO7), is  
written into the location specified on the address pins (A0  
through A19). If Byte High Enable (BHE) is LOW, then data  
from the IO pins (IO8 through IO15) is written into the location  
specified on the address pins (A0 through A19).  
To read from the device, take Chip Enables (CE1 LOW and  
CE2 HIGH) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW,  
then data from memory appears on IO8 to IO15. See the “Truth  
Table” on page 10 for a complete description of read and write  
modes.  
Functional Description[1]  
The CY62167E is a high performance CMOS static RAM  
organized as 1M words by 16 bits/2M words by 8 bits. This  
device features advanced circuit design to provide an ultra low  
active current. This is ideal for providing More Battery Life™  
(MoBL®) in portable applications such as cellular telephones.  
The device also has an automatic power down feature that  
reduces power consumption by 99% when addresses are not  
toggling. Place the device into standby mode when deselected  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
1M × 16 / 2M x 8  
IO0–IO7  
RAM ARRAY  
A 3  
IO8–IO15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE2  
CE  
1
POWER DOWN  
CIRCUIT  
CE  
1
OE  
BHE  
BLE  
BLE  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 001-15607 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 07, 2007  
[+] Feedback  
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