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CY62167DV30LL-70ZIT PDF预览

CY62167DV30LL-70ZIT

更新时间： 2024-11-24 19:55:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 202K
描述
Standard SRAM, 1MX16, 70ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, TSOP1-48

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CY62167DV30LL-70ZIT 技术参数

生命周期：Obsolete零件包装代码：TSOP1
包装说明：TSOP1,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.71
最长访问时间：70 nsJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：18.4 mm
内存密度：16777216 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：12 mmBase Number Matches：1

CY62167DV30LL-70ZIT 数据手册

 浏览型号CY62167DV30LL-70ZIT的Datasheet PDF文件第2页浏览型号CY62167DV30LL-70ZIT的Datasheet PDF文件第3页浏览型号CY62167DV30LL-70ZIT的Datasheet PDF文件第4页浏览型号CY62167DV30LL-70ZIT的Datasheet PDF文件第5页浏览型号CY62167DV30LL-70ZIT的Datasheet PDF文件第6页浏览型号CY62167DV30LL-70ZIT的Datasheet PDF文件第7页 
CY62167DV30  
MoBL®  
16-Mbit (1M x 16) Static RAM  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE1HIGH or CE2  
LOW), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a Write operation (CE1 LOW, CE2 HIGH and WE  
LOW).  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V – 3.60V  
• Ultra-low active power  
— Typical active current: 2 mA @ f = 1 MHz  
— Typical active current: 18.5 mA @ f = fmax (45 ns  
speed)  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A19). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A19).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball BGA and 48-pin TSOPI  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table at the back of this data  
sheet for a complete description of Read and Write modes.  
Functional Description[1]  
The CY62167DV30 is a high-performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
1M × 16  
RAM Array  
I/O0 – I/O7  
I/O8 – I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
CE2  
BHE  
CE  
BLE  
1
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05328 Rev. *F  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised December 20, 2004  
1234567...12

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