Datasheet > CY62167E_09

CY62167E_09

更新时间： 2024-11-20 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	538K
描述
16-Mbit (1M x 16 / 2M x 8) Static RAM

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CY62167E_09 数据手册

CY62167E MoBL^®

16-Mbit (1M x 16 / 2M x 8) Static RAM

(CE₁HIGH, or CE₂LOW, or both BHE and BLE are HIGH).

The input and output pins (IO₀through IO₁₅) are placed in a

high impedance state when:

Features

• Configurable as 1M x 16 or as 2M x 8 SRAM

• Very high speed: 45 ns

• The device is deselected (CE₁HIGH or CE₂LOW)

• Outputs are disabled (OE HIGH)

• Wide voltage range: 4.5V–5.5V

• Ultra low standby power

• Both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH) or

— Typical standby current: 1.5 µA

— Maximum standby current: 12 µA

• Ultra low active power

• A write operation is in progress (CE₁LOW, CE₂HIGH, and

WE LOW)

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

— Typical active current: 2.2 mA @ f = 1 MHz

• Easy memory expansion with CE₁, CE₂, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Offered in 48-pin TSOP I package

(BLE) is LOW, then data from IO pins (IO₀through IO₇), is

written into the location specified on the address pins (A₀

through A₁₉). If Byte High Enable (BHE) is LOW, then data

from the IO pins (IO₈through IO₁₅) is written into the location

specified on the address pins (A₀through A₁₉).

To read from the device, take Chip Enables (CE₁LOW and

CE₂HIGH) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins appears on IO₀to IO₇. If Byte High Enable (BHE) is LOW,

then data from memory appears on IO₈to IO₁₅. See the “Truth

Table” on page 10 for a complete description of read and write

modes.

Functional Description^[1]

The CY62167E is a high performance CMOS static RAM

organized as 1M words by 16 bits/2M words by 8 bits. This

device features advanced circuit design to provide an ultra low

active current. This is ideal for providing More Battery Life™

(MoBL^®) in portable applications such as cellular telephones.

The device also has an automatic power down feature that

reduces power consumption by 99% when addresses are not

toggling. Place the device into standby mode when deselected

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

1M × 16 / 2M x 8

IO₀–IO₇

RAM ARRAY

A ₃

IO₈–IO₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BYTE

BHE

CE₂

POWER DOWN

CIRCUIT

BHE

BLE

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 001-15607 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 07, 2007

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与CY62167E_09相关器件

型号	品牌	获取价格	描述	数据表
CY62167E_10	CYPRESS	获取价格	16-Mbit (1 M × 16 / 2 M × 8) Static RAM
CY62167E_11	CYPRESS	获取价格	16-Mbit (1 M x 16 / 2 M x 8) Static RAM Automatic power-down when deselected
CY62167E_13	CYPRESS	获取价格	16-Mbit (1 M x 16 / 2 M x 8) Static RAM
CY62167ELL	CYPRESS	获取价格	16-Mbit (1 M × 16 / 2 M × 8) Static RAM
CY62167ELL-45ZXI	CYPRESS	获取价格	16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167ELL-45ZXI	INFINEON	获取价格	Asynchronous SRAM
CY62167ELL-45ZXIT	INFINEON	获取价格	Asynchronous SRAM
CY62167ESL-55FNXI	CYPRESS	获取价格	Standard SRAM, 1MX16, 55ns, CMOS, PBGA60, WLCSP-60
CY62167EV18	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167EV18_11	CYPRESS	获取价格	16 Mbit (1M x 16) Static RAM Automatic power down when deselected

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