Datasheet > CY62146E_08

CY62146E_08

更新时间： 2024-11-19 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	309K
描述
4-Mbit (256K x 16) Static RAM

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CY62146E_08 数据手册

CY62146E MoBL^®

4-Mbit (256K x 16) Static RAM

mode reduces power consumption by more than 99% when

deselected (CE HIGH). The input and output pins (IO₀through

IO₁₅) are placed in a high impedance state when:

Features

■ Very high speed: 45 ns

■ Deselected (CE HIGH)

■ Wide voltage range: 4.5V–5.5V

■ Outputs are disabled (OE HIGH)

■ Ultra low standby power

❐ Typical standby current: 1 μA

❐ Maximum standby current: 7 μA

■ Both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH)

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

■ Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇) is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

is written into the location specified on the address pins (A₀

through A₁₇).

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

)

■ Available in Pb-free 44-pin TSOP II package

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See Table 1 for a complete description

of read and write modes.

Functional Description

The CY62146E is a high performance CMOS static RAM

organized as 256K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. It is

ideal for providing More Battery Life™ (MoBL^®) in portable appli-

cations such as cellular telephones. The device also has an

automatic power down feature that reduces power consumption

when addresses are not toggling. Placing the device into standby

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

256K x 16

RAM Array

IO₀–IO₇

IO₈–IO₁₅

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-07970 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 01, 2008

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与CY62146E_08相关器件

型号	品牌	获取价格	描述	数据表
CY62146E_09	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146E_11	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146E_1106	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM Automatic power down when deselected
CY62146E_13	CYPRESS	获取价格	4-Mbit (256 K x 16) Static RAM
CY62146ELL	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ELL-45ZSXA	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ELL-45ZSXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ELL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62146ELL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62146ESL	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM

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