Datasheet > CY62146E_1106

CY62146E_1106

更新时间： 2024-11-19 09:42:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	248K
描述
4-Mbit (256K x 16) Static RAM Automatic power down when deselected

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62146E_1106 数据手册

CY62146E MoBL^

4-Mbit (256K x 16) Static RAM

applications such as cellular telephones. The device also has an

automatic power down feature that reduces power consumption

when addresses are not toggling. Placing the device into standby

mode reduces power consumption by more than 99% when

deselected (CE HIGH). The input and output pins (I/O₀through

I/O₁₅) are placed in a high impedance state when the device is

deselected (CE HIGH), the outputs are disabled (OE HIGH),

both Byte High Enable and Byte Low Enable are disabled (BHE,

BLE HIGH) or during a write operation (CE LOW and WE LOW).

Features

■ Very high speed: 45 ns

■ Wide voltage range: 4.5 V to 5.5 V

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 7 A

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇) is written into the location

specified on the address pins (A₀through A₁₇). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₇).

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See Table for a complete description

of read and write modes.

■ Available in Pb-free 44-pin thin small outline package (TSOP)

II package

Functional Description

The CY62146E is a high performance CMOS static RAM

organized as 256K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. It is

ideal for providing More Battery Life (MoBL^) in portable

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

256K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-07970 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 29, 2011

12 3 4 5 6 7...14

中文翻译

下载PDF

与CY62146E_1106相关器件

型号	品牌	获取价格	描述	数据表
CY62146E_13	CYPRESS	获取价格	4-Mbit (256 K x 16) Static RAM
CY62146ELL	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ELL-45ZSXA	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ELL-45ZSXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ELL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62146ELL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62146ESL	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ESL_08	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ESL_09	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146ESL_11	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM Automatic power down when deselected

与CY62146E_1106相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62146E_1106

CY62146E_1106 数据手册

与CY62146E_1106相关器件

与CY62146E_1106相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62146E_1106

CY62146E_1106 数据手册

与CY62146E_1106相关器件

与CY62146E_1106相关文章

您还可以找

您在本页遇到什么问题？