Datasheet > CY62146EV30

CY62146EV30

更新时间： 2024-11-19 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	526K
描述
4-Mbit (256K x 16) Static RAM

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CY62146EV30 数据手册

CY62146EV30 MoBL^®

4-Mbit (256K x 16) Static RAM

reduces power consumption by 80% when addresses are not

toggling. The device can also be put into standby mode

reducing power consumption by more than 99% when

deselected (CE HIGH). The input and output pins (IO₀through

IO₁₅) are placed in a high impedance state when:

Features

• Very high speed: 45 ns

• Wide voltage range: 2.20V–3.60V

• Pin compatible with CY62146DV30

• Ultra low standby power

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

— Typical standby current: 1 µA

• Both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH)

— Maximum standby current: 7 µA

• Ultra low active power

• Write operation is active (CE LOW and WE LOW)

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

Write to the device by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,

then data from IO pins (IO₀through IO₇), is written into the

location specified on the address pins (A₀through A₁₇). If Byte

High Enable (BHE) is LOW, then data from IO pins (IO₈

through IO₁₅) is written into the location specified on the

address pins (A₀through A₁₇).

• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II

packages

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

If Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the “Truth Table” on page 9 for a

complete description of read and write modes.

Functional Description ^[1]

The CY62146EV30 is a high performance CMOS static RAM

organized as 256K words by 16 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

Product Portfolio

Power Dissipation

Speed

(ns)

Product

V_CCRange (V)

Operating I_CC(mA)

Standby I_SB2(µA)

f = 1 MHz

f = f_max

Min

Typ ^[2]

Max

Typ ^[2]

Max

Typ ^[2]

Max

Typ ^[2]

Max

CY62146EV30LL

2.2

3.0

3.6

45 ns

2.5

Notes:

1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V , T = 25°C.

CC(typ)

Cypress Semiconductor Corporation

Document #: 38-05567 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 26, 2007

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与CY62146EV30相关器件

型号	品牌	获取价格	描述	数据表
CY62146EV30_09	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146EV30LL	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146EV30LL-45BVXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62146EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62146EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62146EV30LL-45ZSXA	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146EV30LL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62146EV30LL-45ZSXI	CYPRESS	获取价格	4-Mbit (256K x 16) Static RAM
CY62146EV30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM

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