Datasheet > CY62146G30-45ZSXA

CY62146G30-45ZSXA

更新时间： 2024-11-20 14:56:47

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
19页	486K
描述
Asynchronous SRAM

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数据手册

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CY62146G MoBL^®Automotive

4-Mbit (256K words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

4-Mbit (256K words

× 16 bit) Static RAM with Error-Correcting Code (ECC)

Features

Functional Description

■ AEC-Q100 qualified

■ High speed: 45 ns

CY62146G is high-performance CMOS low-power (MoBL)

SRAM devices with embedded ECC.

Device is accessed by asserting the chip enable (CE) input LOW.

■ Temperature Range

❐ Automotive-A: -40 C to +85 C

Data writes are performed by asserting the Write Enable (WE)

input LOW, while providing the data on I/O₀through I/O₁₅and

address on A₀through A₁₇pins. The Byte High Enable (BHE)

and Byte Low Enable (BLE) inputs control write operations to the

upper and lower bytes of the specified memory location. BHE

controls I/O₈through I/O₁₅and BLE controls I/O₀through I/O₇.

■ Ultra-low standby power

❐ Typical standby current: 3.5 A

■ Embedded ECC for single-bit error correction^[1]

■ Voltage range: 2.2 V to 3.6 V, 4.5 V to 5.5 V

■ 1.0-V data retention

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on the I/O lines (I/O₀through I/O₁₅).

Byte accesses can be performed by asserting the required byte

enable signal (BHE or BLE) to read either the upper byte or the

lower byte of data from the specified address location.

■ TTL-compatible inputs and outputs

■ Pb-free 44-pin TSOP II package

All I/Os (I/O₀through I/O₁₅) are placed in a HI-Z state when the

device is deselected (CE HIGH), or control signals are

de-asserted (OE, BLE, BHE).

The logic block diagram is on page 2.

Product Portfolio

Power Dissipation

Features and Options

(see Pin Configuration –

CY62146G on page 4)

Operating I_CC(mA)

Speed

Product

Range

V_CCRange (V)

Standby, I_SB2(µA)

(ns)

f = f_max

Typ^[2]

Max

Typ^[2]

Max

CY62146G30 Single Chip Enable

CY62146G

Automotive-A

2.2 V–3.6 V

4.5 V–5.5 V

3.5

8.7

Notes

1. This device does not support automatic write-back on error detection.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V) and V = 5 V

(for V range of 4.5 V–5.5 V), T = 25 °C.

Cypress Semiconductor Corporation

Document Number: 002-03594 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 24, 2017

12 3 4 5 6 7...19

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与CY62146G30-45ZSXA相关器件

型号	品牌	获取价格	描述	数据表
CY62146G30-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY62146G30-45ZSXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, TSOP2-44
CY62146G30-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62146G-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY62146G-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY62146G-45ZSXI	CYPRESS	获取价格	Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, TSOP2-44
CY62146G-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62146GE	CYPRESS	获取价格	4-Mbit (256K words Ã 16 bit) Static RAM with
CY62146GE18	CYPRESS	获取价格	4-Mbit (256K words Ã 16 bit) Static RAM with
CY62146GE30	CYPRESS	获取价格	4-Mbit (256K words Ã 16 bit) Static RAM with

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