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CY62146G30-45ZSXI PDF预览

CY62146G30-45ZSXI

更新时间： 2024-11-19 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
22页 460K
描述
Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, TSOP2-44

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CY62146G30-45ZSXI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSOP2,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：2.25最长访问时间：45 ns
JESD-30 代码：R-PDSO-G44长度：18.415 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
座面最大高度：1.194 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

CY62146G30-45ZSXI 数据手册

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CY62146G/CY62146GE  
CY62146GSL/CY62146GESL MoBL®  
4-Mbit (256K words × 16 bit) Static RAM  
with Error-Correcting Code (ECC)  
4-Mbit (256K words  
× 16 bit) Static RAM with Error-Correcting Code (ECC)  
devices are accessed by asserting both chip enable inputs – CE1  
as low and CE2 as HIGH.  
Features  
■ High speed: 45 ns/55 ns  
Data writes are performed by asserting the Write Enable (WE)  
input LOW, while providing the data on I/O0 through I/O15 and  
address on A0 through A17 pins. The Byte High Enable (BHE)  
and Byte Low Enable (BLE) inputs control write operations to the  
upper and lower bytes of the specified memory location. BHE  
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.  
■ Ultra-low standby power  
❐ Typical standby current: 3.5 A  
❐ Maximum standby current: 8.7 A  
■ Embedded ECC for single-bit error correction[1]  
■ Widevoltage range: 1.65 V to2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V  
■ 1.0-V data retention  
Data reads are performed by asserting the Output Enable (OE)  
input and providing the required address on the address lines.  
Read data is accessible on the I/O lines (I/O0 through I/O15).  
Byte accesses can be performed by asserting the required byte  
enable signal (BHE or BLE) to read either the upper byte or the  
lower byte of data from the specified address location.  
■ TTL-compatible inputs and outputs  
■ Error indication (ERR) pin to indicate 1-bit error detection and  
correction  
■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages  
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the  
device is deselected (CE HIGH for a single chip enable device  
and CE1 HIGH/CE2 LOW for a dual chip enable device), or  
control signals are deasserted (OE, BLE, BHE).  
Functional Description  
CY62146G/CY62146GE and CY62146GSL/CY62146GESL are  
high-performance CMOS low-power (MoBL) SRAM devices with  
embedded ECC. Both devices are offered in single and dual chip  
enable options and in multiple pin configurations. The  
CY62146GE/CY62146GESL device includes an ERR pin that  
signals an error-detection and correction event during a read  
cycle. The CY62146GSL/CY62146GESL[1] device supports a  
wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V.  
On the CY62146GE/CY62146GESL devices, the detection and  
correction of a single-bit error in the accessed location is  
indicated by the assertion of the ERR output (ERR = HIGH)[2]  
.
See  
the  
Truth  
Table  
–
CY62146G/CY62146GE/CY62146GSL/CY62146GESL  
page 17 for a complete description of read and write modes.  
on  
The logic block diagrams are on page 2.  
Devices with a single chip enable input are accessed by  
asserting the chip enable (CE) input LOW. Dual chip enable  
Product Portfolio  
Power Dissipation  
Operating ICC, (mA)  
Features and  
Options  
(see the Pin  
Configurations  
section)  
Standby, ISB2 (µA)  
Product[3]  
Range  
VCC Range (V) Speed (ns)  
f = fmax  
Typ[4]  
Max  
Typ[4]  
Max  
CY62146G(E)18  
CY62146G(E)30  
CY62146G(E)  
Industrial  
1.65 V–2.2 V  
2.2 V–3.6 V  
4.5 V–5.5 V  
55  
45  
15  
15  
20  
20  
3.5  
3.5  
10  
Single or dual  
Chip Enables  
8.7  
Optional ERR  
pin  
CY62146G(E)SL[5]  
2.2 V–3.6 V and  
4.5 V–5.5 V  
Notes  
1. Datasheet specifications are not guaranteed for V in the range of 3.6 V to 4.5 V.  
CC  
2. This device does not support automatic write-back on error detection.  
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.  
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),  
CC  
CC  
V
= 3 V (for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC  
CC  
CC  
A
5. Datasheet specifications are not guaranteed for V in the range of 3.6 V to 4.5 V.  
CC  
Cypress Semiconductor Corporation  
Document Number: 001-95420 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 26, 2017  
 
 
 
 
 
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CY62146G30-45ZSXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62146EV30LL-45ZSXI CYPRESS

完全替代

 4-Mbit (256K x 16) Static RAM

与CY62146G30-45ZSXI相关器件

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CY62146G-45ZSXA INFINEON

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 		Asynchronous SRAM
CY62146G-45ZSXAT INFINEON

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 		Asynchronous SRAM
CY62146G-45ZSXI CYPRESS

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 		Standard SRAM, 256KX16, 45ns, CMOS, PDSO44, TSOP2-44
CY62146G-45ZSXI INFINEON

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 		Asynchronous SRAM
CY62146GE CYPRESS

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 		4-Mbit (256K words × 16 bit) Static RAM with
CY62146GE18 CYPRESS

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 		4-Mbit (256K words × 16 bit) Static RAM with
CY62146GE30 CYPRESS

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 		4-Mbit (256K words × 16 bit) Static RAM with
CY62146GE30-45BVXI CYPRESS

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 		Standard SRAM, 256KX16, 45ns, CMOS, PBGA48, VFBGA-48
CY62146GE30-45BVXI INFINEON

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 		Asynchronous SRAM
CY62146GE30-45ZSXI INFINEON

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 		Asynchronous SRAM

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