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CY62146EV30_09 PDF预览

CY62146EV30_09

更新时间: 2024-11-19 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 444K
描述
4-Mbit (256K x 16) Static RAM

CY62146EV30_09 数据手册

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CY62146EV30 MoBL®  
4-Mbit (256K x 16) Static RAM  
current. Ultra low active current is ideal for providing More  
Battery Life(MoBL®) in portable applications such as cellular  
telephones. The device also has an automatic power down  
feature that significantly reduces power consumption by 80  
percent when addresses are not toggling.The device can also be  
put into standby mode reducing power consumption by more  
than 99 percent when deselected (CE HIGH). The input and  
output pins (I/O0 through I/O15) are placed in a high impedance  
state when: the device is deselected (CE HIGH), outputs are  
disabled (OE HIGH), both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH), or a write operation is in  
progress (CE LOW and WE LOW).  
Features  
Very High Speed: 45 ns  
Temperature Ranges  
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
Wide Voltage Range: 2.20V–3.60V  
Pin Compatible with CY62146DV30  
Ultra Low Standby Power  
Typical standby current: 1 μA  
Maximum standby current: 7 μA  
To write to the device, take Chip Enable (CE ) and Write Enable  
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A17). If Byte High  
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A17).  
Ultra Low Active Power  
Typical active current: 2 mA at f = 1 MHz  
Easy Memory Expansion with CE and OE Features  
Automatic Power Down when Deselected  
CMOS for Optimum Speed and Power  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appears on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the “Truth Table” on page 9 for a  
complete description of read and write modes.  
Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II  
Packages  
Functional Description  
The CY62146EV30 is a high performance CMOS static RAM  
organized as 256K words by 16 bits. This device features an  
advanced circuit design designed to provide an ultra low active  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
256K x 16  
RAM Array  
IO0–IO7  
IO8–IO15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05567 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 23, 2009  
[+] Feedback  

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