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74HC137N,652 PDF预览

74HC137N,652

更新时间: 2024-11-02 20:41:23
品牌 Logo 应用领域
恩智浦 - NXP 驱动双倍数据速率光电二极管逻辑集成电路
页数 文件大小 规格书
19页 108K
描述
74HC137N

74HC137N,652 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.55
其他特性:ADDRESS LATCHES系列:HC/UH
输入调节:LATCHEDJESD-30 代码:R-PDIP-T16
JESD-609代码:e4长度:19.025 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:54 ns
传播延迟(tpd):285 ns认证状态:Not Qualified
座面最大高度:4.2 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.62 mm
Base Number Matches:1

74HC137N,652 数据手册

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74HC137  
3-to-8 line decoder, demultiplexer with address latches;  
inverting  
Rev. 03 — 11 November 2004  
Product data sheet  
1. General description  
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power  
Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address  
inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit  
storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active  
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present  
at the inputs before this transition, is stored in the latches. Further address changes are  
ignored as long as LE remains HIGH.  
The output enable input (E1 and E2) controls the state of the outputs independent of the  
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.  
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state  
systems and strobed (stored address) applications in bus oriented systems.  
2. Features  
Combines 3-to-8 decoder with 3-bit latch  
Multiple input enable for easy expansion or independent controls  
Active LOW mutually exclusive outputs  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  
 
 

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