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74HC138D PDF预览

74HC138D

更新时间: 2024-09-17 14:58:19
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
9页 207K
描述
3-to-8 Line Decoder, SOIC16

74HC138D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.54系列:HC/UH
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
长度:9.9 mm逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):225 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

74HC138D 数据手册

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74HC138D  
CMOS Digital Integrated Circuits Silicon Monolithic  
74HC138D  
1. Functional Description  
3-to-8 Line Decoder  
2. General  
The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology.  
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power  
dissipation.  
When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7)  
will go low.  
When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all  
outputs go high.  
G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory  
systems.  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
3. Features  
(1) High speed: tpd = 16 ns (typ.) at VCC = 5 V  
(2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  
(3) Balanced propagation delays: tPLH tPHL  
(4) Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V  
4. Packaging  
SOIC16  
Start of commercial production  
2016-03  
©2016 Toshiba Corporation  
2016-08-04  
Rev.3.0  
1

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