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74HC138BQ-Q100 PDF预览

74HC138BQ-Q100

更新时间: 2024-11-07 11:12:03
品牌 Logo 应用领域
安世 - NEXPERIA 驱动逻辑集成电路
页数 文件大小 规格书
15页 268K
描述
3-to-8 line decoder/demultiplexer; invertingProduction

74HC138BQ-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
风险等级:5.58系列:HC/UH
输入调节:STANDARDJESD-30 代码:R-PQCC-N16
JESD-609代码:e4长度:3.5 mm
逻辑集成电路类型:OTHER DECODER/DRIVER湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):225 ns筛选级别:AEC-Q100
座面最大高度:1 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:2.5 mmBase Number Matches:1

74HC138BQ-Q100 数据手册

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74HC138-Q100; 74HCT138-Q100  
3-to-8 line decoder/demultiplexer; inverting  
Rev. 5 — 13 August 2021  
Product data sheet  
1. General description  
The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs  
(A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable  
inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.  
This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder  
with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by  
using one of the active LOW enable inputs as the data input and the remaining enable inputs as  
strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface  
inputs to voltages in excess of VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 2.0 to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Demultiplexing capability  
Multiple input enable for easy expansion  
Ideal for memory chip select decoding  
Active LOW mutually exclusive outputs  
Input levels:  
For 74HC138-Q100: CMOS level  
For 74HCT138-Q100: TTL level  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
Multiple package options  
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of  
solder joints  
 
 

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