Datasheet > 74F112SJX

74F112SJX

更新时间： 2024-09-12 23:24:07

品牌	Logo	应用领域
其他 - ETC		触发器
页数	文件大小	规格书
7页	83K
描述
J-K-Type Flip-Flop

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数据手册

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74F112SJX 数据手册

April 1988

Revised September 2000

74F112

Dual JK Negative Edge-Triggered Flip-Flop

Simultaneous LOW signals on S_Dand C_Dforce both Q and

Q HIGH.

General Description

The 74F112 contains two independent, high-speed JK flip-

flops with Direct Set and Clear inputs. Synchronous state

changes are initiated by the falling edge of the clock. Trig-

gering occurs at a voltage level of the clock and is not

directly related to the transition time. The J and K inputs

can change when the clock is in either state without affect-

ing the flip-flop, provided that they are in the desired state

during the recommended setup and hold times relative to

the falling edge of the clock. A LOW signal on S_Dor C_D

Asynchronous Inputs:

LOW input to S_Dsets Q to HIGH level

LOW input to C_Dsets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C_Dand S_Dmakes both Q

and Q HIGH

prevents clocking and forces Q or Q HIGH, respectively.

Ordering Code:

Order Number Package Number

Package Description

74F112SC

74F112SJ

74F112PC

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009472

www.fairchildsemi.com

12 3 4 5 6 7

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与74F112SJX相关器件

型号	品牌	获取价格	描述	数据表
74F112SJX_NL	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDSO16,
74F112SPC	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F112SPCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F112VCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113	FAIRCHILD	获取价格	Dual JK Negative Edge-Triggered Flip-Flop
74F113	NXP	获取价格	Dual J-K negative edge-triggered flip-flops without reset
74F113D	YAGEO	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113DC	FAIRCHILD	获取价格	暂无描述
74F113DCQM	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP14,
74F113DCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output