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74F114 PDF预览

74F114

更新时间: 2024-11-30 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器时钟
页数 文件大小 规格书
6页 58K
描述
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

74F114 数据手册

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April 1988  
Revised August 1999  
74F114  
Dual JK Negative Edge-Triggered Flip-Flop  
with Common Clocks and Clears  
Simultaneous LOW signals on SD and CD force both Q and  
Q HIGH.  
General Description  
The 74F114 contains two high-speed JK flip-flops with  
common Clock and Clear inputs. Synchronous state  
changes are initiated by the falling edge of the clock. Trig-  
gering occurs at a voltage level of the clock and is not  
directly related to the transition time. The J and K inputs  
can change when the clock is in either state without affect-  
ing the flip-flop, provided that they are in the desired state  
during the recommended setup and hold times relative to  
the falling edge of the clock. A LOW signal on SD or CD  
Asynchronous Inputs:  
LOW input to SD sets Q to HIGH level  
LOW input to CD sets Q to LOW level  
Clear and Set are independent of Clock  
Simultaneous LOW on CD and SD  
makes both Q and Q HIGH  
prevents clocking and forces Q or Q HIGH, respectively.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F114SC  
74F114PC  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009474  
www.fairchildsemi.com  

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