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74F113SJX PDF预览

74F113SJX

更新时间: 2024-09-14 23:24:07
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 76K
描述
J-K-Type Flip-Flop

74F113SJX 数据手册

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April 1988  
Revised September 2000  
74F113  
Dual JK Negative Edge-Triggered Flip-Flop  
transferred to the outputs on the falling edge of the clock  
pulse.  
General Description  
The 74F113 offers individual J, K, Set and Clock inputs.  
When the clock goes HIGH the inputs are enabled and  
data may be entered. The logic level of the J and K inputs  
may be changed when the clock pulse is HIGH and the flip-  
flop will perform according to the Truth Table as long as  
minimum setup and hold times are observed. Input data is  
Asynchronous input:  
LOW input to SD sets Q to HIGH level  
Set is independent of clock  
Ordering Code:  
Order Number Package Number  
Package Description  
74F113SC  
74F113SJ  
74F113PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009473  
www.fairchildsemi.com  

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