Datasheet > 74F114

74F114

更新时间： 2024-09-15 04:28:47

品牌	Logo	应用领域
恩智浦 - NXP		触发器时钟
页数	文件大小	规格书
6页	51K
描述
Dual J-K negative edge-triggered flip-flop with common clock and reset

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中文翻译

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数据手册

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74F114 数据手册

Philips Semiconductors

Product specification

Dual J-K negative edge-triggered flip-flop

with common clock and reset

74F114

DESCRIPTION

PIN CONFIGURATION

The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with

common clock and reset inputs, features individual J, K, Clock (CP),

Set (SD) and Reset (RD) inputs, true and complementary outputs.

The SD and RD inputs, when Low, set or reset the outputs as shown

in the Function Table regardless of the level at the other inputs.

13 CP

12 K1

11 J1

SD0

A High level on the clock (CP) input enables the J and K inputs and

data will be accepted. The logic levels and data will be accepted.

The logic levels at the J and K inputs may be allowed to change

while the CP is High and flip-flop will perform according to the

Function Table as long as minimum setup and hold times are

observed. Output changes are initiated by the High-to-Low transition

of the CP.

10 SD1

GND

SF00110

ORDERING INFORMATION

TYPICAL

COMMERCIAL RANGE

= 5V ±10%,

SUPPLY CURRENT

(TOTAL)

TYPE

TYPICAL f

MAX

DESCRIPTION

PKG. DWG. #

amb

= 0°C to +70°C

74F114

100MHz

15mA

14-pin plastic DIP

14-pin plastic SO

N74F114N

SOT27-1

N74F114D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

J0, J1

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

20µA/0.6mA

J inputs

K inputs

1.0/1.0

1.0/5.0

1.0/10.0

1.0/8.0

50/33

K0, K1

20µA/0.6mA

SD0, SD1

Set inputs (active Low)

Reset input (active Low)

Clock Pulse input (active falling edge)

Data outputs

20µA/3.0mA

20µA/6.0mA

20µA/4.8mA

Q0, Q0; Q1, Q1

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

IEC/IEEE SYMBOL

SD0

RD0

SD1

Q1 Q1

Q0 Q0

= Pin 14

GND = Pin 7

SF00112

SF00111

1996 Mar 14

853–0340 16572

12 3 4 5 6

中文翻译

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与74F114相关器件

型号	品牌	获取价格	描述	数据表
74F114D	YAGEO	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114DC	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114DC	ROCHESTER	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114DCQM	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDIP14,
74F114DCQM	ROCHESTER	获取价格	J-K Flip-Flop
74F114DCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114D-T	YAGEO	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114L1C	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114L1CQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114PC	FAIRCHILD	获取价格	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

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