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74F113SCX

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74F113SCX 数据手册

April 1988

Revised September 2000

74F113

Dual JK Negative Edge-Triggered Flip-Flop

transferred to the outputs on the falling edge of the clock

pulse.

General Description

The 74F113 offers individual J, K, Set and Clock inputs.

When the clock goes HIGH the inputs are enabled and

data may be entered. The logic level of the J and K inputs

may be changed when the clock pulse is HIGH and the flip-

flop will perform according to the Truth Table as long as

minimum setup and hold times are observed. Input data is

Asynchronous input:

LOW input to S_Dsets Q to HIGH level

Set is independent of clock

Ordering Code:

Order Number Package Number

Package Description

74F113SC

74F113SJ

74F113PC

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009473

www.fairchildsemi.com

12 3 4 5 6 7

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型号	品牌	获取价格	描述	数据表
74F113SDC	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113SDCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113SJ	FAIRCHILD	获取价格	Dual JK Negative Edge-Triggered Flip-Flop
74F113SJX	ETC	获取价格	J-K-Type Flip-Flop
74F113SPC	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113SPCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113VC	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113VCQR	FAIRCHILD	获取价格	J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114	FAIRCHILD	获取价格	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
74F114	NXP	获取价格	Dual J-K negative edge-triggered flip-flop with common clock and reset