生命周期: | Obsolete | 零件包装代码: | DIP |
包装说明: | DIP, | 针数: | 14 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.68 | 系列: | F/FAST |
JESD-30 代码: | R-CDIP-T14 | 逻辑集成电路类型: | J-K FLIP-FLOP |
位数: | 2 | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 70 °C |
最低工作温度: | 输出极性: | COMPLEMENTARY | |
封装主体材料: | CERAMIC, METAL-SEALED COFIRED | 封装代码: | DIP |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
传播延迟(tpd): | 7 ns | 认证状态: | Not Qualified |
最大供电电压 (Vsup): | 5.25 V | 最小供电电压 (Vsup): | 4.75 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | TTL | 温度等级: | COMMERCIAL |
端子形式: | THROUGH-HOLE | 端子位置: | DUAL |
触发器类型: | NEGATIVE EDGE | 最小 fmax: | 125 MHz |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74F113SJ | FAIRCHILD |
获取价格 |
Dual JK Negative Edge-Triggered Flip-Flop | |
74F113SJX | ETC |
获取价格 |
J-K-Type Flip-Flop | |
74F113SPC | FAIRCHILD |
获取价格 |
J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output | |
74F113SPCQR | FAIRCHILD |
获取价格 |
J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output | |
74F113VC | FAIRCHILD |
获取价格 |
J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output | |
74F113VCQR | FAIRCHILD |
获取价格 |
J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output | |
74F114 | FAIRCHILD |
获取价格 |
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears | |
74F114 | NXP |
获取价格 |
Dual J-K negative edge-triggered flip-flop with common clock and reset | |
74F114D | YAGEO |
获取价格 |
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output | |
74F114DC | FAIRCHILD |
获取价格 |
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output |