5秒后页面跳转
74F113SJ PDF预览

74F113SJ

更新时间: 2024-11-30 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 63K
描述
Dual JK Negative Edge-Triggered Flip-Flop

74F113SJ 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.71
Is Samacsys:N系列:F/FAST
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:80000000 Hz最大I(ol):0.02 A
位数:2功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):19 mA
传播延迟(tpd):7 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:5.3 mm最小 fmax:80 MHz
Base Number Matches:1

74F113SJ 数据手册

 浏览型号74F113SJ的Datasheet PDF文件第2页浏览型号74F113SJ的Datasheet PDF文件第3页浏览型号74F113SJ的Datasheet PDF文件第4页浏览型号74F113SJ的Datasheet PDF文件第5页浏览型号74F113SJ的Datasheet PDF文件第6页 
April 1988  
Revised July 1999  
74F113  
Dual JK Negative Edge-Triggered Flip-Flop  
transferred to the outputs on the falling edge of the clock  
pulse.  
General Description  
The 74F113 offers individual J, K, Set and Clock inputs.  
When the clock goes HIGH the inputs are enabled and  
data may be entered. The logic level of the J and K inputs  
may be changed when the clock pulse is HIGH and the flip-  
flop will perform according to the Truth Table as long as  
minimum setup and hold times are observed. Input data is  
Asynchronous input:  
LOW input to SD sets Q to HIGH level  
Set is independent of clock  
Ordering Code:  
Order Number Package Number  
Package Description  
74F113SC  
74F113SJ  
74F113PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009473  
www.fairchildsemi.com  

与74F113SJ相关器件

型号 品牌 获取价格 描述 数据表
74F113SJX ETC

获取价格

J-K-Type Flip-Flop
74F113SPC FAIRCHILD

获取价格

J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113SPCQR FAIRCHILD

获取价格

J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113VC FAIRCHILD

获取价格

J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F113VCQR FAIRCHILD

获取价格

J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114 FAIRCHILD

获取价格

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
74F114 NXP

获取价格

Dual J-K negative edge-triggered flip-flop with common clock and reset
74F114D YAGEO

获取价格

J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114DC FAIRCHILD

获取价格

J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output
74F114DC ROCHESTER

获取价格

J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output