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74AUP1T45GW PDF预览

74AUP1T45GW

更新时间: 2024-01-05 21:19:01
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
33页 167K
描述
Low-power dual supply translating transceiver; 3-state

74AUP1T45GW 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
风险等级:5.63其他特性:WITH DIRECTION CONTROL
系列:AUP/ULP/VJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
逻辑集成电路类型:BUS TRANSCEIVER湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):40.5 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.1 V标称供电电压 (Vsup):1.4 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mmBase Number Matches:1

74AUP1T45GW 数据手册

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74AUP1T45  
NXP Semiconductors  
Low-power dual supply translating transceiver; 3-state  
Table 7.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ Max  
Unit  
[2]  
IOZ  
OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO  
;
-
-
-
-
-
-
-
-
±0.1  
±0.2  
±0.2  
±0.2  
±0.2  
±0.2  
±0.2  
µA  
current  
V
CC(A) = VCC(B) = 1.1 V to 3.6 V  
A port; VI or VO = 0 V to 3.6 V;  
CC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V  
B port; VI or VO = 0 V to 3.6 V;  
CC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V  
DIR input; VI or VO = 0 V to 3.6 V;  
CC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V  
A port; VI or VO = 0 V to 3.6 V;  
CC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V  
B port; VI or VO = 0 V to 3.6 V;  
CC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V  
DIR input; VI or VO = 0 V to 3.6 V;  
CC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V  
IOFF  
power-off  
-
-
-
-
-
-
µA  
µA  
µA  
µA  
µA  
µA  
leakage current  
V
V
V
IOFF  
additional  
power-off  
V
leakage current  
V
V
[1]  
[1]  
[1]  
ICC  
supply current  
A port; VI = GND or VCCI; IO = 0 A  
VCC(A) = VCC(B) = 1.1 V to 3.6 V  
VCC(A) = 3.6 V; VCC(B) = 0 V  
-
-
-
-
0.5  
0.5  
-
µA  
µA  
µA  
-
VCC(A) = 0 V; VCC(B) = 3.6 V  
0
B port; VI = GND or VCCI; IO = 0 A  
VCC(A) = VCC(B) = 1.1 V to 3.6 V  
VCC(A) = 3.6 V; VCC(B) = 0 V  
-
-
-
-
-
0.5  
-
µA  
µA  
µA  
µA  
0
-
VCC(A) = 0 V; VCC(B) = 3.6 V  
0.5  
0.5  
A plus B port (ICC(A) + ICC(B)); IO = 0 A;  
-
VI = GND or VCCI  
;
VCC(A) = VCC(B) = 1.1 V to 3.6 V  
ICC  
additional supply A port; VCC(A) = VCC(B) = 3.3 V;  
-
-
-
-
-
-
40  
40  
40  
µA  
µA  
µA  
current  
A port at VCC(A) 0.6 V;  
DIR at VCC(A); B port = open  
B port; VCC(A) = VCC(B) = 3.3 V;  
B port at VCC(B) 0.6 V;  
DIR at GND; A port = open  
DIR input; VCC(A) = VCC(B) = 3.3 V;  
A port at VCC(A) or GND; B port = open;  
DIR at VCC(A) 0.6 V  
CI  
input  
capacitance  
DIR input; VI = GND or VCC(A)  
VCC(A) = VCC(B) = 1.1 V to 3.6 V  
;
-
-
0.9  
2.0  
-
-
pF  
pF  
[1][2]  
CI/O  
input/output  
capacitance  
A and B port; suspend mode; VCCI = 0 V;  
CCO = 1.1 V to 3.6 V; VO = VCCO or GND  
V
74AUP1T45_1  
© NXP B.V. 2006. All rights reserved.  
Product data sheet  
Rev. 01 — 18 October 2006  
6 of 33  

74AUP1T45GW 替代型号

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完全替代

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