5秒后页面跳转
74AUP1T57GN PDF预览

74AUP1T57GN

更新时间: 2023-09-03 20:28:26
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
17页 260K
描述
Low-power configurable gate with voltage-level translatorProduction

74AUP1T57GN 数据手册

 浏览型号74AUP1T57GN的Datasheet PDF文件第2页浏览型号74AUP1T57GN的Datasheet PDF文件第3页浏览型号74AUP1T57GN的Datasheet PDF文件第4页浏览型号74AUP1T57GN的Datasheet PDF文件第5页浏览型号74AUP1T57GN的Datasheet PDF文件第6页浏览型号74AUP1T57GN的Datasheet PDF文件第7页 
74AUP1T57  
Low-power configurable gate with voltage-level translator  
Rev. 7 — 26 January 2022  
Product data sheet  
1. General description  
The 74AUP1T57 is a configurable multiple function gate with level translating, Schmitt-trigger  
inputs. The device can be configured as any of the following logic functions AND, OR, NAND,  
NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC  
or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels  
in 3.3 V applications.  
This device ensures very low static and dynamic power consumption across the entire VCC range  
from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The  
IOFF circuitry disables the output, preventing the potentially damaging backflow current through the  
device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 2.3 V to 3.6 V  
High noise immunity  
Low static power consumption; ICC = 1.5 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial power-down mode operation  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74AUP1T57GW  
74AUP1T57GM  
74AUP1T57GN  
74AUP1T57GS  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
TSSOP6  
plastic thin shrink small outline package; 6 leads;  
body width 1.25 mm  
SOT363-2  
XSON6  
XSON6  
XSON6  
plastic extremely thin small outline package; no leads; SOT886  
6 terminals; body 1 × 1.45 × 0.5 mm  
extremely thin small outline package; no leads;  
6 terminals; body 0.9 × 1.0 × 0.35 mm  
SOT1115  
extremely thin small outline package; no leads;  
6 terminals; body 1.0 × 1.0 × 0.35 mm  
SOT1202  
 
 
 

与74AUP1T57GN相关器件

型号 品牌 描述 获取价格 数据表
74AUP1T57GS NEXPERIA Low-power configurable gate with voltage-level translatorProduction

获取价格

74AUP1T57GW NEXPERIA Low-power configurable gate with voltage-level translatorProduction

获取价格

74AUP1T57GW NXP Low-power configurable gate with voltage-level translator

获取价格

74AUP1T57GW,125 NXP 74AUP1T57 - Low-power configurable gate with voltage-level translator TSSOP 6-Pin

获取价格

74AUP1T57GW-G NXP IC,LOGIC GATE,2-IN MULTI-FUNC,CMOS,TSSOP,6PIN,PLASTIC

获取价格

74AUP1T58 NXP Low-power configurable gate with voltage-level translator

获取价格