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74AUP1T57GW-G

更新时间： 2024-02-15 03:33:11

品牌	Logo	应用领域
恩智浦 - NXP		转换器电平转换器
页数	文件大小	规格书
17页	95K
描述
IC,LOGIC GATE,2-IN MULTI-FUNC,CMOS,TSSOP,6PIN,PLASTIC

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74AUP1T57GW-G 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSSOP, TSSOP6,.08	Reach Compliance Code：	unknown
风险等级：	5.84	JESD-30 代码：	R-PDSO-G6
负载电容（CL）：	30 pF	最大I（ol）：	0.0027 A
端子数量：	6	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP6,.08
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TAPE AND REEL	电源：	2.5/3.3 V
Prop。Delay @ Nom-Sup：	11.9 ns	认证状态：	Not Qualified
施密特触发器：	YES	子类别：	Gates
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

74AUP1T57GW-G 数据手册

74AUP1T57

Low-power conﬁgurable gate with voltage-level translator

Rev. 02 — 3 August 2009

Product data sheet

1. General description

The 74AUP1T57 provides low-power, low-voltage conﬁgurable logic gate functions. The

output state is determined by eight patterns of 3-bit input. The user can choose the logic

functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected

to V_CCor GND.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 2.3 V to 3.6 V.

The 74AUP1T57 is designed for logic-level translation applications with input switching

levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single

2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from

3.6 V to 2.3 V.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the

entire V_CCrange.

2. Features

I Wide supply voltage range from 2.3 V to 3.6 V

I High noise immunity

I ESD protection:

N HBM JESD22-A114E Class 3A exceeds 5000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Low static power consumption; I_CC= 1.5 µA (maximum)

I Latch-up performance exceeds 100 mA per JESD 78 Class II

I Inputs accept voltages up to 3.6 V

I Low noise overshoot and undershoot < 10 % of V_CC

I I_OFFcircuitry provides partial Power-down mode operation

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...17

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