Datasheet > 74AUP1T57GN

74AUP1T57GN

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
恩智浦 - NXP		栅输入元件光电二极管
页数	文件大小	规格书
20页	132K
描述
IC AUP/ULP/V SERIES, 3-INPUT MAJORITY LOGIC GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6, Gate

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AUP1T57GN 数据手册

74AUP1T57

Low-power configurable gate with voltage-level translator

Rev. 4 — 1 December 2011

Product data sheet

1. General description

The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The

output state is determined by eight patterns of 3-bit input. The user can choose the logic

functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected

to V_CCor GND.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 2.3 V to 3.6 V.

The 74AUP1T57 is designed for logic-level translation applications with input switching

levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single

2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from

3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across

the entire V_CCrange.

2. Features and benefits

 Wide supply voltage range from 2.3 V to 3.6 V

 High noise immunity

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 1.5 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...20

中文翻译

下载PDF

与74AUP1T57GN相关器件

型号	品牌	获取价格	描述	数据表
74AUP1T57GS	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T57GW	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T57GW	NXP	获取价格	Low-power configurable gate with voltage-level translator
74AUP1T57GW,125	NXP	获取价格	74AUP1T57 - Low-power configurable gate with voltage-level translator TSSOP 6-Pin
74AUP1T57GW-G	NXP	获取价格	IC,LOGIC GATE,2-IN MULTI-FUNC,CMOS,TSSOP,6PIN,PLASTIC
74AUP1T58	NXP	获取价格	Low-power configurable gate with voltage-level translator
74AUP1T58GF	NXP	获取价格	Low-power configurable gate with voltage-level translator
74AUP1T58GF,132	NXP	获取价格	74AUP1T58 - Low-power configurable gate with voltage-level translator SON 6-Pin
74AUP1T58GF-H	NXP	获取价格	IC,LOGIC GATE,2-IN MULTI-FUNC,CMOS,LLCC,6PIN,PLASTIC
74AUP1T58GM	NXP	获取价格	Low-power configurable gate with voltage-level translator