74AUP1T97GF

更新时间： 2024-02-05 11:38:51

品牌	Logo	应用领域
恩智浦 - NXP		转换器电平转换器
页数	文件大小	规格书
17页	89K
描述
Low-power configurable gate with voltage-level translator

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74AUP1T97GF 数据手册

74AUP1T97

Low-power conﬁgurable gate with voltage-level translator

Rev. 01 — 25 October 2007

Product data sheet

1. General description

The 74AUP1T97 provides low-power, low-voltage conﬁgurable logic gate functions. The

output state is determined by eight patterns of 3-bit input. The user can choose the logic

functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to

V_CCor GND.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 2.3 V to 3.6 V.

The 74AUP1T97 is designed for logic-level translation applications with input switching

levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single

2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from

3.6 V to 2.3 V.

This device is fully speciﬁed for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across

the entire V_CCrange.

2. Features

■ Wide supply voltage range from 2.3 V to 3.6 V

■ High noise immunity

■ ESD protection:

◆ HBM JESD22-A114E Class 3A exceeds 5000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101C exceeds 1000 V

■ Low static power consumption; I_CC= 1.5 µA (maximum)

■ Latch-up performance exceeds 100 mA per JESD 78 Class II

■ Inputs accept voltages up to 3.6 V

■ Low noise overshoot and undershoot < 10 % of V_CC

■ I_OFFcircuitry provides partial Power-down mode operation

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...17

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型号	品牌	获取价格	描述	数据表
74AUP1T97GF,132	NXP	获取价格	74AUP1T97 - Low-power configurable gate with voltage-level translator SON 6-Pin
74AUP1T97GF/S500	NXP	获取价格	SPECIALTY LOGIC CIRCUIT, PDSO6
74AUP1T97GF/S500,132	NXP	获取价格	Logic Circuit, CMOS, PDSO6
74AUP1T97GM	NXP	获取价格	Low-power configurable gate with voltage-level translator
74AUP1T97GM	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T97GM,132	NXP	获取价格	74AUP1T97 - Low-power configurable gate with voltage-level translator SON 6-Pin
74AUP1T97GN	NXP	获取价格	暂无描述
74AUP1T97GN	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T97GN,132	NXP	获取价格	74AUP1T97 - Low-power configurable gate with voltage-level translator SON 6-Pin
74AUP1T97GS	NXP	获取价格	SPECIALTY LOGIC CIRCUIT, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, XSON-6