Datasheet > 74AUP1T97GN,132

74AUP1T97GN,132

更新时间： 2024-01-29 21:37:34

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
20页	208K
描述
74AUP1T97 - Low-power configurable gate with voltage-level translator SON 6-Pin

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74AUP1T97GN,132 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SON
包装说明：	0.90 X 1.00 MM, 0.35 MM HEIGHT, SOT-1115, XSON-6	针数：	6
Reach Compliance Code：	compliant	风险等级：	5.66
Is Samacsys：	N	Base Number Matches：	1

74AUP1T97GN,132 数据手册

74AUP1T97

Low-power configurable gate with voltage-level translator

Rev. 4 — 15 August 2012

Product data sheet

1. General description

The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The

output state is determined by eight patterns of 3-bit input. The user can choose the logic

functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to

_CCor GND.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 2.3 V to 3.6 V.

The 74AUP1T97 is designed for logic-level translation applications with input switching

levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single

2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from

3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across

the entire V_CCrange.

2. Features and benefits

 Wide supply voltage range from 2.3 V to 3.6 V

 High noise immunity

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 1.5 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...20

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74AUP1T97GS	NXP	获取价格	SPECIALTY LOGIC CIRCUIT, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, XSON-6
74AUP1T97GS	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T97GW	NXP	获取价格	Low-power configurable gate with voltage-level translator
74AUP1T97GW	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T97GW,125	NXP	获取价格	74AUP1T97 - Low-power configurable gate with voltage-level translator TSSOP 6-Pin
74AUP1T97GW-Q100	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T97GX	NEXPERIA	获取价格	Low-power configurable gate with voltage-level translatorProduction
74AUP1T97L6X	ONSEMI	获取价格	Low Power Configurable Gate
74AUP1T97L6X	FAIRCHILD	获取价格	Low Power Configurable Gate with Voltage-Level Translator
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