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74AUP1Z04GM,132 PDF预览

74AUP1Z04GM,132

更新时间: 2024-01-03 20:35:04
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
28页 245K
描述
74AUP1Z04 - Low-power X-tal driver with enable and internal transistor SON 6-Pin

74AUP1Z04GM,132 技术参数

生命周期:Active零件包装代码:SON
包装说明:VSON,针数:6
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.36系列:AUP/ULP/V
JESD-30 代码:R-PDSO-N6JESD-609代码:e3
长度:1.45 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:1
功能数量:1端口数量:2
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):20.1 ns
认证状态:Not Qualified座面最大高度:0.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1 mm
Base Number Matches:1

74AUP1Z04GM,132 数据手册

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74AUP1Z04  
Low-power X-tal driver with enable and internal resistor  
Rev. 5 — 9 August 2012  
Product data sheet  
1. General description  
The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with  
enable circuitry and an internal bias resistor to provide a device optimized for use in  
crystal oscillator applications.  
When not in use the EN input can be driven HIGH, putting the device in a low power  
disable mode with X1 pulled HIGH via RPU, X2 set LOW and Y set HIGH.Schmitt trigger  
action at the EN input makes the circuit tolerant to slower input rise and fall times across  
the entire VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF at output Y.  
The IOFF circuitry disables the output Y, preventing the damaging backflow current through  
the device when it is powered down.  
The integration of the two devices into the 74AUP1Z04 produces the benefits of a  
compact footprint, lower power dissipation and stable operation over a wide range of  
frequency and temperature.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Latch-up performance exceeds 100 mA per JESD78B Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation at output Y  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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