Datasheet > 74AUP2G00

74AUP2G00

更新时间： 2023-12-06 19:51:56

品牌	Logo	应用领域
美台 - DIODES		栅
页数	文件大小	规格书
9页	254K
描述
Dual 2 Input NAND Logic Gates

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AUP2G00 数据手册

74AUP2G00

DUAL NAND GATE

Description

Pin Assignments

The Advanced Ultra Low Power (AUP) CMOS logic family is designed

for low power and extended battery life in portable applications.

(Top View)

The 74AUP2G00 is a dual two input NAND gate. Both gates have

push-pull outputs designed for operation over a power supply range

of 0.8V to 3.6V. The device is fully specified for partial power down

applications using I_OFF. The I_OFFcircuitry disables the output

preventing damaging current backflow when the device is powered

down. Each gate performs the positive Boolean function:

Y = A •B or Y = A + B

X2-DFN1210-8

Features

Applications

•

Advanced Ultra Low Power (AUP) CMOS

Supply Voltage Range from 0.8V to 3.6V

±4mA Output Drive at 3.0V

•

Suited for Battery and Low Power Needs

Wide Array of Products Such as:

Tablets, E-readers

Low Static Power Consumption

I_CC< 0.9µA

Cell Phones, Personal Navigation/GPS

MP3 Players, Cameras, Video Recorders

PCs, Ultrabooks, Notebooks, Netbooks

Computer Peripherals, Hard Drives, SSD, CD/DVD ROM

TV, DVD, DVR, Set-Top Box

•

Low Dynamic Power Consumption

C_PD= 6 pF (Typical at 3.6V)

Schmitt Trigger Action at all inputs makes the circuit tolerant

for slower input rise and fall time. The hysteresis is typically

250 mV at V_CC= 3.0V

•

I_OFFSupports Partial-Power-Down Mode Operation

ESD Protection Exceeds JESD 22

2000-V Human Body Model (A114)

Exceeds 1000-V Charged Device Model (C101)

Latch-Up Exceeds 100mA per JESD 78, Class I

Leadless Packages Named per JESD30E

•

Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)

Halogen and Antimony Free. “Green” Device (Note 3)

Notes:

1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.

2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,

"Green" and Lead-free.

3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl)

and <1000ppm antimony compounds.

1 of 9

www.diodes.com

January 2015

74AUP2G00

Document number: DS36139 Rev 2 - 2

12 3 4 5 6 7...9

下载PDF

与74AUP2G00相关器件

型号	品牌	描述	获取价格	数据表
74AUP2G00DC	NXP	Low-power dual 2-input NAND gate	获取价格
74AUP2G00DC	NEXPERIA	Low-power dual 2-input NAND gateProduction	获取价格
74AUP2G00DC-G	NXP	Low-power dual 2-input NAND gate	获取价格
74AUP2G00DC-Q100	NEXPERIA	Low-power dual 2-input NAND gateProduction	获取价格
74AUP2G00GD	NXP	Low-power dual 2-input NAND gate	获取价格
74AUP2G00GD,125	NXP	74AUP2G00 - Low-power dual 2-input NAND gate SON 8-Pin	获取价格