Datasheet > 74AUP1T97GW

74AUP1T97GW

更新时间： 2024-09-25 11:12:19

品牌	Logo	应用领域
安世 - NEXPERIA		栅光电二极管逻辑集成电路触发器
页数	文件大小	规格书
19页	279K
描述
Low-power configurable gate with voltage-level translatorProduction

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74AUP1T97GW 数据手册

74AUP1T97

Low-power configurable gate with voltage-level translator

Rev. 9 — 17 July 2023

Product data sheet

1. General description

The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger

inputs. The device can be configured as any of the following logic functions MUX, AND, OR,

NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to

V_CCor GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic

levels in 3.3 V applications. This device ensures very low static and dynamic power consumption

across the entire V_CCrange from 2.3 V to 3.6 V. This device is fully specified for partial power down

applications using I_OFF. The I_OFFcircuitry disables the output, preventing the potentially damaging

backflow current through the device when it is powered down.

2. Features and benefits

•

Wide supply voltage range from 2.3 V to 3.6 V

•

CMOS low power dissipation

High noise immunity

Overvoltage tolerant inputs to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial power-down mode operation

Latch-up performance exceeds 100 mA per JESD 78 Class II

Low static power consumption; I_CC= 1.5 μA (maximum)

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

•

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...19

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