生命周期: | Active | 包装说明: | XSON-6 |
Reach Compliance Code: | unknown | 风险等级: | 5.65 |
系列: | AUP/ULP/V | JESD-30 代码: | S-PDSO-N6 |
长度: | 1 mm | 逻辑集成电路类型: | LOGIC CIRCUIT |
功能数量: | 1 | 端子数量: | 6 |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | VSON |
封装形状: | SQUARE | 封装形式: | SMALL OUTLINE, VERY THIN PROFILE |
座面最大高度: | 0.5 mm | 最大供电电压 (Vsup): | 3.6 V |
最小供电电压 (Vsup): | 2.3 V | 标称供电电压 (Vsup): | 2.5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子形式: | NO LEAD |
端子节距: | 0.35 mm | 端子位置: | DUAL |
宽度: | 1 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74AUP1T97GM | NXP |
获取价格 |
Low-power configurable gate with voltage-level translator | |
74AUP1T97GM | NEXPERIA |
获取价格 |
Low-power configurable gate with voltage-level translatorProduction | |
74AUP1T97GM,132 | NXP |
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74AUP1T97 - Low-power configurable gate with voltage-level translator SON 6-Pin | |
74AUP1T97GN | NXP |
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暂无描述 | |
74AUP1T97GN | NEXPERIA |
获取价格 |
Low-power configurable gate with voltage-level translatorProduction | |
74AUP1T97GN,132 | NXP |
获取价格 |
74AUP1T97 - Low-power configurable gate with voltage-level translator SON 6-Pin | |
74AUP1T97GS | NXP |
获取价格 |
SPECIALTY LOGIC CIRCUIT, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, XSON-6 | |
74AUP1T97GS | NEXPERIA |
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Low-power configurable gate with voltage-level translatorProduction | |
74AUP1T97GW | NXP |
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Low-power configurable gate with voltage-level translator | |
74AUP1T97GW | NEXPERIA |
获取价格 |
Low-power configurable gate with voltage-level translatorProduction |