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UPA1728G PDF预览

UPA1728G

更新时间: 2024-02-04 18:19:29
品牌 Logo 应用领域
其他 - ETC 晶体晶体管开关脉冲
页数 文件大小 规格书
8页 69K
描述
TRANSISTOR | MOSFET | N-CHANNEL | 60V V(BR)DSS | 9A I(D) | SO

UPA1728G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.84
配置:Single最大漏极电流 (Abs) (ID):9 A
FET 技术:METAL-OXIDE SEMICONDUCTOR工作模式:ENHANCEMENT MODE
最高工作温度:150 °C极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):2 W子类别:FET General Purpose Power
表面贴装:YESBase Number Matches:1

UPA1728G 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µ
PA1728  
SWITCHING  
N-CHANNEL POWER MOS FET  
DESCRIPTION  
The µPA1728 is N-Channel MOS Field Effect Transistor  
designed for high current switching applications.  
PACKAGE DRAWING (Unit: mm)  
8
5
1, 2, 3  
4
5, 6, 7, 8 ; Drain  
; Source  
; Gate  
FEATURES  
Single chip type  
Low on-state resistance  
DS(on)1  
R
DS(on)2  
R
DS(on)3  
R
GS  
D
= 19 mTYP. (V = 10 V, I = 4.5 A)  
6.0 ±0.3  
4.4  
1
4
GS  
D
= 23 mTYP. (V = 4.5 V, I = 4.5 A)  
5.37 Max.  
0.8  
GS  
D
= 24 mTYP. (V = 4.0 V, I = 4.5 A)  
iss  
iss  
Low C : C = 1700 pF TYP.  
Built-in G-S protection diode  
0.5 ±0.2  
0.10  
Small and surface mount package (Power SOP8)  
1.27 0.78 Max.  
+0.10  
–0.05  
0.40  
0.12 M  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
µPA1728G  
Power SOP8  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)  
GS  
DSS  
Drain to Source Voltage (V = 0 V)  
V
60  
±20  
±9  
V
EQUIVALENT CIRCUIT  
DS  
GSS  
Gate to Source Voltage (V = 0 V)  
V
V
D(DC)  
Drain Current (DC)  
I
A
Drain  
Drain Current (Pulse) Note1  
D(pulse)  
I
±36  
2.0  
150  
A
Note2  
A
Body  
Diode  
Total Power Dissipation (T = 25°C)  
T
P
W
°C  
Gate  
ch  
T
Channel Temperature  
stg  
T
Storage Temperature  
–55 to + 150 °C  
Gate  
Protection  
Diode  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
AS  
I
9
A
Source  
AS  
E
81  
mJ  
Notes 1. PW 10 µs, Duty cycle 1%  
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm  
ch  
DD  
G
GS  
3. Starting T = 25°C, V = 30 V, R = 25 , T = 20 0 V  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage  
exceeding the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
Date Published March 2002 NS CP(K)  
Printed in Japan  
G14321EJ3V0DS00 (3rd edition)  
The mark shows major revised points.  
1999,2000,2001  
©

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