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UPA1744TP

更新时间： 2024-02-18 07:06:22
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管开关脉冲光电二极管
页数 文件大小 规格书
7页 76K
描述
SWITCHING N-CHANNEL POWER MOSFET

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中文翻译

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UPA1744TP 技术参数

生命周期：Obsolete零件包装代码：SOT
包装说明：SMALL OUTLINE, R-PDSO-G8针数：8
Reach Compliance Code：unknownECCN代码：EAR99
风险等级：5.84雪崩能效等级（Eas）：10 mJ
外壳连接：DRAIN配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：100 V最大漏极电流 (ID)：10 A
最大漏源导通电阻：0.03 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-PDSO-G8JESD-609代码：e6
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
最大脉冲漏极电流 (IDM)：30 A认证状态：Not Qualified
表面贴装：YES端子面层：TIN BISMUTH
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

UPA1744TP 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µ PA1744TP  
SWITCHING  
N-CHANNEL POWER MOS FET  
PACKAGE DRAWING (Unit: mm)  
DESCRIPTION  
The µ PA1744TP is N-channel MOS FET device that features a  
low on-state resistance and excellent switching characteristics, and  
designed for high voltage applications such as DC/DC converter.  
8
5
1, 2, 3  
4
5, 6, 7, 8, 9: Drain  
: Source  
: Gate  
FEATURES  
• Low on-state resistance  
6.0 ±0.3  
1
4
0.8 ±0.2  
4.4 ±0.15  
+0.17  
–0.2  
5.2  
RDS(on) = 30 mΩ MAX. (VGS = 10 V, ID = 5.0 A)  
• Low input capacitance  
S
Ciss = 3400 pF TYP. (VDS = 10 V, VGS = 0 V)  
• Built-in gate protection diode  
0.10  
S
1.27 TYP.  
+0.10  
0.40  
0.12 M  
–0.05  
• Small and surface mount package (Power HSOP8)  
1
4
2.0 ±0.2  
9
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
4.1 MAX.  
µ PA1744TP  
Power HSOP8  
8
5
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, all terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) (TC = 25°C)  
Drain Current (pulse) Note1  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
100  
V
±20  
V
EQUIVALENT CIRCUIT  
±10  
A
±30  
A
Drain  
Total Power Dissipation (TC = 25°C)  
Total Power Dissipation (TA = 25°C) Note2  
Channel Temperature  
39  
W
W
°C  
°C  
A
PT2  
3.0  
Body  
Diode  
Gate  
Tch  
150  
Storage Temperature  
Tstg  
−55 to +150  
10  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
Gate  
IAS  
Protection  
Diode  
Source  
EAS  
10  
mJ  
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%  
2. Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm  
3. Starting Tch = 25°C, VDD = 50 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 µH  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage exceeding  
the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G16410EJ1V0DS00 (1st edition)  
Date Published March 2003 NS CP(K)  
Printed in Japan  
2002  
1234567

中文翻译

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