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UPA1741

更新时间: 2024-02-16 06:56:37
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UPA1741TP Data Sheet | Data Sheet[04/2003]

UPA1741 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.84
配置:Single最大漏极电流 (Abs) (ID):5 A
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-609代码:e6
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):21 W
子类别:FET General Purpose Power表面贴装:YES
端子面层:Tin/Bismuth (Sn98Bi2)Base Number Matches:1

UPA1741 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µ PA1741TP  
SWITCHING  
N-CHANNEL POWER MOS FET  
PACKAGE DRAWING (Unit: mm)  
DESCRIPTION  
The µPA1741TP is N-channel MOS FET device that features a  
low on-state resistance and excellent switching characteristics, and  
designed for high voltage applications such as DC/DC converter.  
8
5
1, 2, 3  
4
5, 6, 7, 8, 9 ; Drain  
; Source  
; Gate  
FEATURES  
High voltage: VDSS = 250 V  
Gate voltage rating: ±30 V  
Low on-state resistance  
6.0 ±0.3  
1
4
0.8 ±0.2  
4.4 ±0.15  
+0.17  
–0.2  
5.2  
RDS(on) = 0.79 MAX. (VGS = 10 V, ID = 2.5 A)  
Low input capacitance  
S
Ciss = 340 pF TYP. (VDS = 10 V, VGS = 0 V)  
Built-in gate protection diode  
Small and surface mount package (Power HSOP8)  
0.10  
S
1.27 TYP.  
+0.10  
–0.05  
0.40  
0.12 M  
1
4
2.0 ±0.2  
9
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
4.1 MAX.  
µPA1741TP  
Power HSOP8  
8
5
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise noted. All terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) (TC = 25°C)  
Drain Current (pulse) Note1  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
250  
±30  
±5.0  
±15  
21  
V
V
EQUIVALENT CIRCUIT  
A
A
Drain  
Total Power Dissipation (TC = 25°C)  
Total Power Dissipation (TA = 25°C)Note2  
Channel Temperature  
W
W
°C  
PT2  
1
Body  
Diode  
Gate  
Tch  
150  
Storage Temperature  
Tstg  
55 to +150 °C  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
Gate  
Protection  
Diode  
IAS  
5.0  
2.5  
5.0  
2.5  
A
mJ  
A
Source  
EAS  
Note4  
Repetitive Avalanche Current  
Repetitive Pulse Avalanche Energy Note4  
IAR  
EAR  
mJ  
Notes 1. PW 10 µs, Duty Cycle 1%  
2. Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm  
3. Starting Tch = 25°C, VDD = 125 V, RG = 25 , L = 100 µH, VGS = 20 0 V  
4. Tch(peak) 150°C, L = 100 µH  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage exceeding  
the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G16373EJ1V0DS00 (1st edition)  
Date Published April 2003 NS CP(K)  
Printed in Japan  
2003  

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